Patents by Inventor Anant Shankar Kamath
Anant Shankar Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869933Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.Type: GrantFiled: August 10, 2021Date of Patent: January 9, 2024Assignee: Texas Instruments IncorporatedInventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
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Patent number: 11863360Abstract: An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.Type: GrantFiled: January 25, 2022Date of Patent: January 2, 2024Assignee: Texas Instruments IncorporatedInventors: Kumar Anurag Shrivastava, Siraj Akhtar, Swaminathan Sankaran, Anant Shankar Kamath
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Publication number: 20230412431Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Sadia Arefin KHAN, Anant Shankar KAMATH, Martin STAEBLER, Vikas Kumar THAWANI
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Patent number: 11841810Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.Type: GrantFiled: April 29, 2021Date of Patent: December 12, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Suvadip Banerjee, Sreeram Subramanyam Nasum, Anant Shankar Kamath
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Patent number: 11809206Abstract: An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.Type: GrantFiled: August 26, 2021Date of Patent: November 7, 2023Assignee: Texas Instruments IncorporatedInventors: Kishalay Datta, Anant Shankar Kamath, Kumar Anurag Shrivastava, Swaminathan Sankaran
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Publication number: 20230336083Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.Type: ApplicationFiled: July 19, 2022Publication date: October 19, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Dushmantha Bandara RAJAPAKSHA, Roland SPERLICH, Anant Shankar KAMATH, Vijayalakshmi DEVARAJAN, Wesley RAY
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Patent number: 11792051Abstract: A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.Type: GrantFiled: June 21, 2021Date of Patent: October 17, 2023Assignee: Texas Instruments IncorporatedInventors: Sadia Arefin Khan, Anant Shankar Kamath, Martin Staebler, Vikas Kumar Thawani
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Publication number: 20230308323Abstract: An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.Type: ApplicationFiled: January 25, 2022Publication date: September 28, 2023Inventors: Kumar Anurag Shrivastava, Siraj Akhtar, Swaminathan Sankaran, Anant Shankar Kamath
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Patent number: 11669475Abstract: An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels.Type: GrantFiled: April 30, 2021Date of Patent: June 6, 2023Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, Rakesh Hariharan, Mark Edward Wentroble
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Patent number: 11671138Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.Type: GrantFiled: September 29, 2021Date of Patent: June 6, 2023Assignee: Texas Instruments IncorporatedInventors: RR Manikandan, Kumar Anurag Shrivastava, Robert Floyd Payne, Anant Shankar Kamath, Swaminathan Sankaran, Kishalay Datta, Siraj Akhtar, Mark Edward Wentroble, Suvadip Banerjee, Rakesh Hariharan, Gurumurti Kailaschandra Avhad
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Publication number: 20230155628Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.Type: ApplicationFiled: January 23, 2023Publication date: May 18, 2023Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
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Patent number: 11630797Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.Type: GrantFiled: June 7, 2021Date of Patent: April 18, 2023Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, Rakesh Hariharan, Vivekkumar Ramanlal Vadodariya, Soumi Paul, Mayank Garg
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Publication number: 20230111096Abstract: In an example, a method of operating a repeater having an isolation barrier to isolate a host side of the repeater from a peripheral side of the repeater, the repeater operable to be coupled to a universal serial bus (USB), includes causing the host side to enter into a suspend mode. The method also includes, responsive to entering the suspend mode, disabling a host isolation transceiver at the host side. The method includes periodically enabling the host isolation transceiver to transmit a data signal from the host side to the peripheral side. The method includes exiting the suspend mode. The method also includes enabling the host isolation transceiver.Type: ApplicationFiled: April 28, 2022Publication date: April 13, 2023Inventors: Rakesh HARIHARAN, Tarunvir SINGH, Anant Shankar KAMATH, Mark Edward WENTROBLE, Christopher Joseph RODRIGUES, Prajwala PUTTAPPA
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Patent number: 11621711Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.Type: GrantFiled: July 13, 2021Date of Patent: April 4, 2023Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, Kanteti Amar, Bharath Kumar Singareddy, Rakesh Hariharan
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Publication number: 20230069663Abstract: An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Kishalay Datta, Anant Shankar Kamath, Kumar Anurag Shrivastava, Swaminathan Sankaran
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Publication number: 20230025757Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.Type: ApplicationFiled: September 29, 2021Publication date: January 26, 2023Inventors: RR Manikandan, Kumar Anurag Shrivastava, Robert Floyd Payne, Anant Shankar Kamath, Swaminathan Sankaran, Kishalay Datta, Siraj Akhtar, Mark Edward Wentroble, Suvadip Banerjee, Rakesh Hariharan, Gurumurti Kailaschandra Avhad
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Publication number: 20230022405Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.Type: ApplicationFiled: July 13, 2021Publication date: January 26, 2023Inventors: Anant Shankar Kamath, Kanteti Amar, Bharath Kumar Singareddy, Rakesh Hariharan
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Publication number: 20230028275Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.Type: ApplicationFiled: July 22, 2021Publication date: January 26, 2023Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
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Patent number: 11563462Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.Type: GrantFiled: July 22, 2021Date of Patent: January 24, 2023Assignee: Texas Instruments IncorporatedInventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
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Publication number: 20220391345Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Anant Shankar KAMATH, Rakesh HARIHARAN, Vivekkumar Ramanlal VADODARIYA, Soumi PAUL, Mayank GARG