Patents by Inventor Anant Shankar Kamath
Anant Shankar Kamath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9698728Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.Type: GrantFiled: December 11, 2013Date of Patent: July 4, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anant Shankar Kamath, Sreeram N S
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Publication number: 20160300907Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.Type: ApplicationFiled: April 7, 2015Publication date: October 13, 2016Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
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Patent number: 9455721Abstract: An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.Type: GrantFiled: December 31, 2014Date of Patent: September 27, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Divyasree J., Anant Shankar Kamath
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Publication number: 20160105187Abstract: An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.Type: ApplicationFiled: December 31, 2014Publication date: April 14, 2016Inventors: Divyasree J., Anant Shankar Kamath
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Publication number: 20140169038Abstract: Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.Type: ApplicationFiled: December 11, 2013Publication date: June 19, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Anant Shankar Kamath, Sreeram N. S.
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Patent number: 8456210Abstract: A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.Type: GrantFiled: December 7, 2010Date of Patent: June 4, 2013Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, SundaraSiva Rao Giduturi
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Patent number: 8446198Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.Type: GrantFiled: April 16, 2010Date of Patent: May 21, 2013Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, Krishnaswamy Nagaraj, Sudheer Kumar Vemulapalli, Jayawardan Janardhanan, Karthik Subburaj, Sujoy Chakravarty, Vikas Sinha
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Patent number: 8411804Abstract: A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.Type: GrantFiled: February 21, 2011Date of Patent: April 2, 2013Assignee: Texas Instruments IncorporatedInventors: Karthik Subburaj, Anant Shankar Kamath, Jayawardan Janardhanan
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Publication number: 20120213314Abstract: A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal.Type: ApplicationFiled: February 21, 2011Publication date: August 23, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Karthik Subburaj, Anant Shankar Kamath, Jayawardan Janardhanan
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Publication number: 20120139595Abstract: A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Anant Shankar Kamath, SundaraSiva Rao Giduturi
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Publication number: 20110254603Abstract: Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: Texas Instruments IncorporatedInventors: Anant Shankar KAMATH, Krishnaswamy NAGARAJ, Sudheer Kumar VEMULAPALLI, Jayawardan JANARDHANAN, Karthik SUBBURAJ, Sujoy CHAKRAVARTY, Vikas SINHA
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Patent number: 7737747Abstract: A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.Type: GrantFiled: August 31, 2007Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventor: Anant Shankar Kamath
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Patent number: 7719369Abstract: A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively proportionate to the most significant bits (MSBs) and least significant bits (LSBs) of a received digital value. The two portions are added to generate an analog output representing the strength of the digital value. In an embodiment, the single DAC contains a set of current sources, with some of the current sources (determined by the value of the MSBs) being connected to provide the corresponding output currents on a first path. Some of the other current sources, determined by a value of the LSBs, are controlled to be connected to provide the corresponding output currents on a second path. The time durations the currents are connected to the second path, are determined by the output of a sigma delta modulator.Type: GrantFiled: September 17, 2008Date of Patent: May 18, 2010Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, Biman Chattopadhyay
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Publication number: 20100066455Abstract: A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively proportionate to the most significant bits (MSBs) and least significant bits (LSBs) of a received digital value. The two portions are added to generate an analog output representing the strength of the digital value. In an embodiment, the single DAC contains a set of current sources, with some of the current sources (determined by the value of the MSBs) being connected to provide the corresponding output currents on a first path. Some of the other current sources, determined by a value of the LSBs, are controlled to be connected to provide the corresponding output currents on a second path. The time durations the currents are connected to the second path, are determined by the output of a sigma delta modulator.Type: ApplicationFiled: September 17, 2008Publication date: March 18, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Anant Shankar Kamath, Biman Chattopadhyay
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Publication number: 20090245439Abstract: An output buffer providing a buffered output signal using multiple power supplies. The output signal is driven using a first power supply during a first interval, and using another (second) power supply during a second interval. In an embodiment, the first power supply is designed to be a high capacity supply, and drives the output signal during a substantial portion of a logic 0 to logic 1 transition. The second power supply is designed to be a low capacity supply, and drives the output during steady states (logic 0/logic 1).Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Anant Shankar Kamath, Jagdish Chand Goyal
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Patent number: 7560962Abstract: Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.Type: GrantFiled: December 12, 2006Date of Patent: July 14, 2009Assignee: Texas Instruments IncorporatedInventor: Anant Shankar Kamath
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Publication number: 20090058480Abstract: A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.Type: ApplicationFiled: August 31, 2007Publication date: March 5, 2009Inventor: Anant Shankar Kamath
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Patent number: 7429895Abstract: Various systems and methods for drift compensation are disclosed. As one example, a system for compensating drift in a control circuit is disclosed that includes at least two control signals. One of the control signals is provided by a circuit that is susceptible to drift. This control signal is provided both to a systems or device under control, and to a detection circuit. The detection circuit is operable to detect a drift in the control signal. In addition, the detection circuit provides another control signal that varies as a function of the drift in the received control signal.Type: GrantFiled: February 28, 2006Date of Patent: September 30, 2008Assignee: Texas Instruments IncorporatedInventors: Prakash Easwaran, Anant Shankar Kamath, Rupak Ghayal, Birman Chattopadhyay, Gopal Krishna Nayak, Sameer Raghavendra Joshi, Mithun Guddethota Neelakant, Subhash Yekanath Pai, Shivaprakash Halagur
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Publication number: 20080136471Abstract: Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Applicant: Texas Instruments IncorporatedInventor: Anant Shankar Kamath
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Patent number: 7177613Abstract: A receiver, implemented with low noise and low distortion, to process an input signal containing signals of interest and unwanted interference signal. In an embodiment, the receiver contains a mixer which generates an intermediate signal in the form of an electric current, and a filter which filters the unwanted interference signals from the intermediate signal. The intermediate signal is centered around a lower frequency compared to a carrier frequency of the input signal. Due to the current mode interface between the mixer and the filter circuit, low noise and low distortion may be attained.Type: GrantFiled: September 30, 2004Date of Patent: February 13, 2007Assignee: Texas Instruments IncorporatedInventors: Anant Shankar Kamath, Gaurav Chandra, Prakash Easwaran