Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.

Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.

Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Abstract: In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.

Abstract: In at least one general aspect, a SiC device can include a drift region of a first conductivity type, a shielding body, and a Schottky region. The SiC device can include a rim having a second conductivity type at least partially surrounding the shielding body and the Schottky region. The SiC device can include a termination region at least partially surrounding the rim and having a doping of the second conductivity type. The termination region can have a transition zone disposed between a first zone and a second zone where the first zone has a top surface lower in depth than a depth of a top surface of the second zone and the transition zone has a recess.

Abstract: In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode.

Abstract: In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide.

Abstract: In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate capacitance. In the SiC trench gate MOSFET, a thick gate oxide can be formed on a bottom surface of the gate trench and a built-in channel, having a vertical portion and a lateral portion, can be formed to electrically connect a vertical inversion-layer channel, such as in a channel stopper layer, to a vertical JFET channel region and a drift region.

Abstract: A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type.

Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Abstract: In one general aspect, an apparatus can include a semiconductor region including a silicon carbide material and a junction termination extension implant region disposed in the semiconductor region. The apparatus can include a low interface state density portion of a dielectric layer having at least a portion in contact with the junction termination extension implant region.

Abstract: In at least one general aspect, a SiC device can include a drift region of a first conductivity type, a shielding body, and a Schottky region. The SiC device can include a rim having a second conductivity type at least partially surrounding the shielding body and the Schottky region. The SiC device can include a termination region at least partially surrounding the rim and having a doping of the second conductivity type. The termination region can have a transition zone disposed between a first zone and a second zone where the first zone has a top surface lower in depth than a depth of a top surface of the second zone and the transition zone has a recess.

Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) crystal having a top surface aligned along a plane and the SiC crystal having an off-orientation direction. The apparatus including a semiconductor device defined within the SiC crystal. The semiconductor device having an outer perimeter where the outer perimeter has a first side aligned along the off-orientation direction and a second side aligned along a direction non-parallel to the off-orientation direction. The first side of the outer perimeter of the semiconductor device having a length longer than the second side of the outer perimeter of the semiconductor device.

Abstract: In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the drift region and a source region disposed in the body region. The apparatus can also include a gate trench disposed in the semiconductor substrate. The apparatus can further include a gate dielectric disposed on a sidewall and a bottom surface of the gate trench, the gate dielectric on the sidewall defining a first interface with the body region and the gate dielectric on the bottom surface defining a second interface with the body region. The apparatus can still further include a gate electrode disposed on the gate dielectric and a lateral channel region disposed in the body region, the lateral channel region being defined along the second interface.

Abstract: In one general aspect, an apparatus can include a semiconductor region including a silicon carbide material and a junction termination extension implant region disposed in the semiconductor region. The apparatus can include a low interface state density portion of a dielectric layer having at least a portion in contact with the junction termination extension implant region.

Abstract: In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide.

Abstract: In one general aspect, an apparatus can include a silicon carbide (SiC) crystal having a top surface aligned along a plane and the SiC crystal having an off-orientation direction. The apparatus including a semiconductor device defined within the SiC crystal. The semiconductor device having an outer perimeter where the outer perimeter has a first side aligned along the off-orientation direction and a second side aligned along a direction non-parallel to the off-orientation direction. The first side of the outer perimeter of the semiconductor device having a length longer than the second side of the outer perimeter of the semiconductor device.

Abstract: In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode.