Abstract: The present disclosure is related to alleviation of at least some of the drawbacks of the previously known implementations and to provide an improved alternative. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a planarized surface.

Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are described. The SiC BJT comprises a collector region, a base region and an emitter region disposed as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically disposed between the first portion and the emitter region in the stack.

Abstract: New designs of high power switching circuits and controller circuits are provided. Principal silicon bipolar switch is connected in parallel to snubber switch that is formed of a wide bandgap material. The snubber switch is activated during at least one of turn-on and turn-off of the principal silicon switch so as to minimize (or reduce) the switching loss and to bypass safe operation area limitations.

Abstract: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.

Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.

Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are described. The SiC BJT comprises a collector region, a base region and an emitter region disposed as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically disposed between the first portion and the emitter region in the stack.

Abstract: The present disclosure is related to alleviation of at least some of the above drawbacks of the prior art and to provide an improved alternative to the prior art. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a surface (of the drift layer) with improved smoothness. Further, at least some of the embodiments are related to a method of manufacturing a power rectifier device with reduced leakage currents.

Abstract: New designs of high power switching circuits and controller circuits are provided. Principal silicon bipolar switch is connected in parallel to snubber switch that is formed of a wide bandgap material. The snubber switch is activated during at least one of turn-on and turn-off of the principal silicon switch so as to minimize (or reduce) the switching loss and to bypass safe operation area limitations.

Abstract: A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type.

Abstract: A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

Abstract: A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT are provided. The SiC BJT comprises an emitter region, a base region and a collector region. The collector region is arranged on a substrate having an off-axis orientation of about 4 degrees or lower. Further, a defect termination layer (DTL) is arranged between the substrate and the collector region. A thickness and a doping level of the DTL are configured to terminate basal plane dislocations in the DTL and reduce the growth of defects from the DTL to the collector region. At least some of the embodiments are advantageous in that SiC BJTs with improved stability are provided. Further, a method of evaluating the degradation performance of a SiC BJT is provided.

Abstract: A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.

Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

Abstract: A lateral field effect transistor for high switching frequencies having a source region layer (4) and a drain region layer (5) laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer (6) of lower doping concentration extending laterally and interconnecting the source region layer (4) and the drain region layer (5). The transistor has a gate electrode (7) arranged to control the properties of the channel layer (6), and a second-conductivity-type base layer (8) arranged under the channel layer (6) at least partially overlapping the gate electrode (7) and at a lateral distance to the drain region layer (5), the highly doped second-conductivity-type base layer (8) being shorted to the source region layer (4).

Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

Abstract: Method for producing a field effect transistor having a source region (9), a drain region and a channel layer (11) interconnecting the source and drain regions, and including the step of providing a sacrificial layer (4) on part of a semiconductor material (1) whose edge is used to define the edge of an implant, such as the source region (9), in the semiconductor material (1), where the edge (4c) of the sacrificial layer (4) is subsequently used to define the edge of a gate (16).

Abstract: A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

Abstract: A junction barrier Schottky diode is provided as having submicron channel width between implant regions by way of a process including the use of spacer technology. On-state resistance is lowered by providing the implant regions in a channel layer having increased dopant concentration.