Patents by Inventor Andrew D. Bailey, III
Andrew D. Bailey, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317412Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF-period, and to assist in the re-striking of the bottom plasma during the ON -period.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
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Publication number: 20230274911Abstract: Methods, systems, apparatuses, and computer programs are presented for controlling etch rate and plasma uniformity using magnetic fields. A substrate processing apparatus includes a vacuum chamber including a processing zone for processing a substrate. The apparatus further includes a magnetic field sensor configured to detect a signal representing a residual magnetic field associated with the vacuum chamber. At least one magnetic field source is configured to generate one or more supplemental magnetic fields through the processing zone of the vacuum chamber. A magnetic field controller is coupled to the magnetic field sensor and the at least one magnetic field source. The magnetic field controller is configured to adjust at least one characteristic of the one or more supplemental magnetic fields, causing the one or more supplemental magnetic fields to reduce the residual magnetic field to a pre-determined value.Type: ApplicationFiled: June 24, 2021Publication date: August 31, 2023Inventor: Andrew D. Bailey, III
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Patent number: 11704463Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.Type: GrantFiled: March 31, 2021Date of Patent: July 18, 2023Assignee: Lam Research CorporationInventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
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Patent number: 11670486Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF-period, and to assist in the re-striking of the bottom plasma during the ON-period.Type: GrantFiled: March 27, 2020Date of Patent: June 6, 2023Assignee: Lam Research CorporationInventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
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Publication number: 20230071249Abstract: Methods, systems, apparatuses, and computer programs are presented for controlling etch rate and plasma uniformity using magnetic fields. A semiconductor substrate processing apparatus includes a vacuum chamber including a processing zone for processing a substrate using capacitively coupled plasma (CCP). The apparatus further includes a magnetic field sensor configured to detect a signal representing a residual magnetic field associated with the vacuum chamber. At least one magnetic field source is configured to generate one or more supplemental magnetic fields through the processing zone of the vacuum chamber. A magnetic field controller is coupled to the magnetic field sensor and the at least one magnetic field source. The magnetic field controller is configured to adjust at least one characteristic of the one or more supplemental magnetic fields, causing the one or more supplemental magnetic fields to reduce the residual magnetic field to a pre-determined value.Type: ApplicationFiled: January 29, 2021Publication date: March 9, 2023Inventors: Scott Briggs, Pratik Mankidy, John P. Holland, Andrew D. Bailey, III
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Patent number: 11594400Abstract: A plasma processing system includes a plasma chamber having a substrate support, and a multi-zone gas injection upper electrode disposed opposite the substrate support. An inner plasma region is defined between the upper electrode and the substrate support. The multi-zone gas injection upper electrode has a plurality of concentric gas injection zones. A confinement structure, which surrounds the inner plasma region, has an upper horizontal wall that interfaces with the outer electrode of the upper electrode. The confinement structure has a lower horizontal wall that interfaces with the substrate support, and includes a perforated confinement ring and a vertical wall that extends from the upper horizontal wall to the lower horizontal wall. The lower surface of the upper horizontal wall, an inner surface of the vertical wall, and an upper surface of the lower horizontal wall define a boundary of an outer plasma region, which surrounds the inner plasma region.Type: GrantFiled: April 10, 2020Date of Patent: February 28, 2023Assignee: Lam Research CorporationInventors: Ryan Bise, Rajinder Dhindsa, Alexei Marakhtanov, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony de la Llera, Darrell Ehrlich
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Publication number: 20230057217Abstract: Gas distribution faceplates are disclosed that feature clusters of gas passages extending from inlet gas ports on a first side thereof to outlet gas ports on a second side thereof. The gas passages may each have at least a portion thereof that is at an oblique angle with respect to a nominal centerline of the gas distribution faceplate, thereby allowing the inlet gas ports for a given cluster of gas passages to be tightly grouped together and the outlet gas ports for that cluster of gas passages to be more widely spaced apart. This allows for a large numbers of gas passages to be used, thereby allowing for a reduction of flow rate through each gas passage and an attendant decrease in gas passage erosion rate, while reducing or eliminating the effects of overlapping wear zones around each outlet gas port.Type: ApplicationFiled: January 28, 2021Publication date: February 23, 2023Inventors: Henry Stephen Povolny, Andrew D. Bailey, III, Anthony de la Llera, Nebiyu Barsula Sermollo, Shawn Tokairin
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Publication number: 20210216695Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.Type: ApplicationFiled: March 31, 2021Publication date: July 15, 2021Inventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
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Patent number: 11056322Abstract: A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed, wherein the dry processing creates at least one gas byproduct. A concentration of the at least one gas byproduct is measured. The concentration of the at least one gas byproduct is used to determine processing rate of the substrate.Type: GrantFiled: August 3, 2017Date of Patent: July 6, 2021Assignee: Lam Research CorporationInventors: Yassine Kabouzi, Luc Albarede, Andrew D. Bailey, III, Jorge Luque, Seonkyung Lee, Thorsten Lill
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Patent number: 11029668Abstract: A system includes sensors, an interface and a controller. The interface receives feedback signals from the sensors. At least some of the sensors are disposed in an electrostatic chuck. The feedback signals are indicative respectively of fields of a heating plate of the electrostatic chuck. The controller, based on the fields and sets of calibration values, estimates values of a first field respectively for multiple points on a substrate. Each of the sets of calibration values corresponds respectively to one of multiple actuators. The calibration values, in each of the sets of calibration values, define amounts of contribution provided by a respective one of the actuators to the first field for the points. The controller changes physical states of the actuators based on the estimated values of the first field of the points to provide a predetermined temperature distribution profile across the electrostatic chuck.Type: GrantFiled: July 9, 2019Date of Patent: June 8, 2021Assignee: Lam Research CorporationInventors: Marcus Musselman, Andrew D. Bailey, III
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Patent number: 11011353Abstract: A substrate support in a substrate processing system includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller. The controller at least one of raises the edge ring to selectively cause the edge ring to engage the substrate and lowers the inner portion to selectively cause the edge ring to engage the substrate. The controller determines when the edge ring engages the substrate and calculates at least one characteristic of the substrate processing system based on the determination of when the edge ring engages the substrate.Type: GrantFiled: January 11, 2017Date of Patent: May 18, 2021Assignee: Lam Research CorporationInventors: Marcus Musselman, Andrew D. Bailey, III, Jon McChesney
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Patent number: 10997345Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.Type: GrantFiled: January 13, 2020Date of Patent: May 4, 2021Assignee: Lam Research CorporationInventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
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Patent number: 10847430Abstract: Methods and systems for using a time-series of spectra to identify endpoint of an etch process. One method includes accessing a virtual carpet that is generated from a time-series of spectra for an etch process. A polynomial with coefficients represents the virtual carpet. The method includes processing a fabrication etch process on a fabrication wafer and generating a carpet defined from a time-series of spectra while processing the fabrication etch process. While the processing the fabrication etch process and generating the carpet, comparing portions of the carpet and the virtual carpet to identify an endpoint metric of the fabrication etch process.Type: GrantFiled: April 16, 2019Date of Patent: November 24, 2020Assignee: Lam Research CorporationInventors: Ye Feng, Prashanth Kumar, Andrew D. Bailey, III
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Patent number: 10763142Abstract: A system for controlling a condition of a wafer processing chamber is disclosed. According the principles of the present disclosure, the system includes memory and a first controller. The memory stores a plurality of profiles of respective ones of a plurality of first control elements. The plurality of first control elements are arranged throughout the chamber. The first controller determines non-uniformities in a substrate processing parameter associated with the plurality of first control elements. The substrate processing parameter is different than the condition of the chamber. The first controller adjusts at least one of the plurality of profiles based on the non-uniformities in the substrate processing parameter and a sensitivity of the substrate processing parameter to the condition.Type: GrantFiled: September 21, 2015Date of Patent: September 1, 2020Assignee: LAM RESEARCH CORPORATIONInventors: Marcus Musselman, Juan Valdivia, III, Hua Xiang, Andrew D. Bailey, III, Yoko Yamaguchi, Qian Fu, Aaron Eppler
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Publication number: 20200243307Abstract: A plasma processing system includes a plasma chamber having a substrate support, and a multi-zone gas injection upper electrode disposed opposite the substrate support. An inner plasma region is defined between the upper electrode and the substrate support. The multi-zone gas injection upper electrode has a plurality of concentric gas injection zones. A confinement structure, which surrounds the inner plasma region, has an upper horizontal wall that interfaces with the outer electrode of the upper electrode. The confinement structure has a lower horizontal wall that interfaces with the substrate support, and includes a perforated confinement ring and a vertical wall that extends from the upper horizontal wall to the lower horizontal wall. The lower surface of the upper horizontal wall, an inner surface of the vertical wall, and an upper surface of the lower horizontal wall define a boundary of an outer plasma region, which surrounds the inner plasma region.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Ryan Bise, Rajinder Dhindsa, Alexei Marakhtanov, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony de la Llera, Darrell Ehrlich
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Publication number: 20200227237Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF-period, and to assist in the re-striking of the bottom plasma during the ON-period.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
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Publication number: 20200218844Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.Type: ApplicationFiled: January 13, 2020Publication date: July 9, 2020Inventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
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Patent number: 10622195Abstract: A system and method of plasma processing includes a plasma processing system including a plasma chamber and a controller coupled to the plasma chamber. The plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric gas injection zones.Type: GrantFiled: April 3, 2012Date of Patent: April 14, 2020Assignee: Lam Research CorporationInventors: Ryan Bise, Rajinder Dhindsa, Alexei Marakhtanov, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony Dela Llera, Darrell Ehrlich
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Patent number: 10585347Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.Type: GrantFiled: December 18, 2018Date of Patent: March 10, 2020Assignee: Lam Research CorporationInventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
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Patent number: 10572697Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.Type: GrantFiled: April 6, 2018Date of Patent: February 25, 2020Assignee: Lam Research CorporationInventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert