Patents by Inventor Andrew D. Bailey, III

Andrew D. Bailey, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553399
    Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to set parameters to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF period, and to assist in the re-striking of the bottom plasma during the ON period.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 4, 2020
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Patent number: 10534257
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 14, 2020
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Richard Wise
  • Publication number: 20190393105
    Abstract: Photoresist features can be characterized by electron microscopy-based metrology. A protective coating may be deposited on the photoresist with no change or minimal change to the dimensions of the underlying photoresist features, where the protective coating may be conformal and formed in a reactor operated under low temperature and low plasma conditions. In some implementations, the protective coating is formed by plasma-enhanced atomic layer deposition. Reliable and accurate profile information of photoresist features can be captured by metrology using the protective coating.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Jea L. Cho, Daniel Anthony Simon, Andrew D. Bailey, III
  • Patent number: 10504704
    Abstract: A substrate etching system includes an etching control module, a filtering module, and an endpoint module. The etching control module selectively begins plasma etching of a substrate within an etching chamber. The filtering module, during the plasma etching of the substrate: receives a signal including endpoint information; decomposes the signal using empirical mode decomposition (EMD); and generates a filtered signal based on results of the EMD. The endpoint module indicates when an endpoint of the plasma etching of the substrate has been reached based on the filtered signal. The etching control module ends the plasma etching of the substrate in response to the indication that the endpoint of the plasma etching of the substrate has been reached.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 10, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Luc Albarede, Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III
  • Publication number: 20190332094
    Abstract: A system includes sensors, an interface and a controller. The interface receives feedback signals from the sensors. At least some of the sensors are disposed in an electrostatic chuck. The feedback signals are indicative respectively of fields of a heating plate of the electrostatic chuck. The controller, based on the fields and sets of calibration values, estimates values of a first field respectively for multiple points on a substrate. Each of the sets of calibration values corresponds respectively to one of multiple actuators. The calibration values, in each of the sets of calibration values, define amounts of contribution provided by a respective one of the actuators to the first field for the points. The controller changes physical states of the actuators based on the estimated values of the first field of the points to provide a predetermined temperature distribution profile across the electrostatic chuck.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Marcus MUSSELMAN, Andrew D. Bailey, III
  • Publication number: 20190311083
    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.
    Type: Application
    Filed: April 6, 2018
    Publication date: October 10, 2019
    Inventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
  • Patent number: 10386828
    Abstract: Disclosed are methods of optimizing a computerized model which relates etched feature profile on a semiconductor device to a set of independent input parameters via the use of a plurality of model parameters. The optimization methods may include modifying the model parameters so that an etch profile generated with the model is such that it reduces a metric indicative of the combined differences between experimental etch profiles resulting from experimental etch processes performed using different sets of values for sets of independent input parameters and computed etch profiles generated from the model and corresponding to the experimental etch profiles. Said metric may be calculated by projecting computed and corresponding experimental etch profiles onto a reduced-dimensional subspace used to calculate a difference between the profiles. Also disclosed herein are systems employing such optimized models, as well as methods of using such models to approximately determine the profile of an etched feature.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 20, 2019
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Juline Shoeb, Alex Paterson, Richard A. Gottscho
  • Patent number: 10386821
    Abstract: A system including a controller, an interface, and a calibration controller. The controller is configured to (i) select a set of fields, and (ii) based on the set of fields, supply control effort to first actuators in zones of a chamber. The interface is configured to receive feedback signals from sensors. The feedback signals are indicative of fields respectively of the zones. The controller is configured to adjust an amount of control effort supplied to the actuators based on the fields. The calibration controller is configured to, based on the fields, generate calibration values for each of the sensors. The calibration values for each of the sensors are indicative of field contributions corresponding respectively to the actuators.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 20, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Marcus Musselman, Andrew D. Bailey, III
  • Publication number: 20190250501
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 15, 2019
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Publication number: 20190244870
    Abstract: Methods and systems for using a time-series of spectra to identify endpoint of an etch process. One method includes accessing a virtual carpet that is generated from a time-series of spectra for an etch process. A polynomial with coefficients represents the virtual carpet. The method includes processing a fabrication etch process on a fabrication wafer and generating a carpet defined from a time-series of spectra while processing the fabrication etch process. While the processing the fabrication etch process and generating the carpet, comparing portions of the carpet and the virtual carpet to identify an endpoint metric of the fabrication etch process.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Ye Feng, Prashanth Kumar, Andrew D. Bailey, III
  • Patent number: 10312121
    Abstract: A substrate support in a substrate processing system includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller. The controller, to selectively cause the edge ring to engage the substrate and tilt the substrate, controls at least one actuator to at least one of raise and lower the edge ring and raise and lower the inner portion of the substrate support. The controller determines an alignment of a measurement device in the substrate processing system based on a signal reflected from a surface of the substrate when the substrate is tilted.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Lam Research Corporation
    Inventors: Marcus Musselman, Andrew D. Bailey, III, Dmitry Opaits
  • Patent number: 10303830
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 28, 2019
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 10262910
    Abstract: Methods and systems for using a time-series of spectra to identify endpoint of an etch process. One method includes accessing a virtual carpet that is formed from a time-series of spectra for the etch process collected during a training operation. And, running a fabrication etch process on a fabrication wafer, such that while the fabrication etch process is performed portions of a carpet defined from a time-series of spectral is generated for the fabrication etch process. Then, comparing the portions of the carpet of the fabrication etch process to the virtual carpet. End pointing is processed for the fabrication etch process when said comparing indicates that a desired metric has been reached for the fabrication wafer. In one example, said portions of the carpet include a current frame of captured spectra and at least one previous frame of captured spectra.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Ye Feng, Prashanth Kumar, Andrew D. Bailey, III
  • Patent number: 10242849
    Abstract: A system and method of identifying a selected process point in a multi-mode pulsing process includes applying a multi-mode pulsing process to a selected wafer in a plasma process chamber, the multi-mode pulsing process including multiple cycles, each one of the cycles including at least one of multiple, different phases. At least one process output variable is collected for a selected at least one of the phases, during multiple cycles for the selected wafer. An envelope and/or a template of the collected at least one process output variable can be used to identify the selected process point. A first trajectory for the collected process output variable of a previous phase can be compared to a second trajectory of the process output variable of the selected phase. A multivariate analysis statistic of the second trajectory can be calculated and used to identify the selected process point.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Yassine Kabouzi, Jorge Luque, Andrew D. Bailey, III, Mehmet Derya Tetiker, Ramkumar Subramanian, Yoko Yamaguchi
  • Publication number: 20190049937
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 10197908
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 10181412
    Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: January 15, 2019
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Mirzafer K. Abatchev, Rajinder Dhindsa, Eric Hudson, Andrew D. Bailey, III
  • Publication number: 20180314148
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Richard Wise
  • Publication number: 20180260509
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 13, 2018
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 10032681
    Abstract: Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals produced by optical energy interacting with features being etched on the substrate; (b) providing a subset of the measured optical signals, wherein the subset is defined by a range where optical signals were determined to correlate with target geometric parameter values for features; (c) applying the subset of optical signals to a model configured to predict the target geometric parameter values from the measured optical signals; (d) determining, from the model, a current value of the target geometric parameter of the features being etched; (e) comparing the current value of the target geometric parameter of the features being etched to an etch process endpoint value for the target geometric parameter; and (f) repeating (a)-(e) until the comparing in (e) indicates that the current value of the target geometric parameter of the features being etched has reach
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: July 24, 2018
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Mehmet Derya Tetiker, Duncan W. Mills