Patents by Inventor Andrew E. Gruber
Andrew E. Gruber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230186423Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: February 7, 2023Publication date: June 15, 2023Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 11605149Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: March 30, 2022Date of Patent: March 14, 2023Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20220222770Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Inventors: Stephen L. MOREIN, Laurent LEFEBVRE, Andrew E. GRUBER, Andi SKENDE
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Patent number: 11328382Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: April 14, 2021Date of Patent: May 10, 2022Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20210233205Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: Stephen L. MOREIN, Laurent LEFEBVRE, Andrew E. GRUBER, Andi SKENDE
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Patent number: 11023996Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: August 28, 2020Date of Patent: June 1, 2021Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20200394750Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Inventors: Stephen L. MOREIN, Laurent LEFEBVRE, Andrew E. GRUBER, Andi SKENDE
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Patent number: 10796400Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: October 14, 2019Date of Patent: October 6, 2020Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 10489876Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: June 27, 2016Date of Patent: November 26, 2019Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 9582846Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: February 5, 2015Date of Patent: February 28, 2017Assignee: ATI TECHNOLOGIES ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20160307356Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 9245496Abstract: This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.Type: GrantFiled: December 21, 2012Date of Patent: January 26, 2016Assignee: QUALCOMM IncorporatedInventors: Andrew E. Gruber, Tao Wang, Shambhoo Khandelwal
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Patent number: 9087410Abstract: In some examples, aspects of this disclosure relate to a method for rendering an image. For example, the method includes generating visibility information indicating visible primitives of the image. The method also includes rendering the image using a binning configuration, wherein the binning configuration is based on the visibility information.Type: GrantFiled: January 17, 2013Date of Patent: July 21, 2015Assignee: QUALCOMM IncorporatedInventors: Avinash Seetharamaiah, Murat Balci, Christopher Paul Frascati, Andrew E. Gruber
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Publication number: 20150154731Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 8931108Abstract: A graphics processing unit (GPU) is configured to access a first memory unit according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to allow the GPU to read data from only an unsecure portion of the first memory unit when the GPU is in the unsecure mode, and configured to allow the GPU to write data only to a secure portion of the first memory unit when the GPU is in the secure mode.Type: GrantFiled: February 18, 2013Date of Patent: January 6, 2015Assignee: QUALCOMM IncorporatedInventors: Colin Christopher Sharp, Sudeep Ravi Kottilingal, Thomas Edwin Frisinger, Andrew E. Gruber
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Patent number: 8860721Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.Type: GrantFiled: March 28, 2006Date of Patent: October 14, 2014Assignee: ATI Technologies ULCInventors: Andrew E. Gruber, Christopher J. Brennan
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Publication number: 20140300613Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 8832417Abstract: This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction identified by a program counter value stored in a program counter register. The control flow instruction may include a target value indicative of a target program counter value for the control flow instruction. The control flow unit may select one of the target program counter value and a minimum resume counter value as a value to load into the program counter register. The minimum resume counter value may be indicative of a smallest resume counter value from a set of one or more resume counter values associated with one or more inactive threads. Each of the one or more resume counter values may be indicative of a program counter value at which a respective inactive thread should be activated.Type: GrantFiled: September 7, 2011Date of Patent: September 9, 2014Assignee: QUALCOMM IncorporatedInventors: Lin Chen, David Rigel Garcia Garcia, Andrew E. Gruber, Guofang Jiao
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Publication number: 20140237609Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a first memory unit according to one of an unsecure mode and a secure mode. The GPU comprises a memory access controller configured to allow the GPU to read data from only an unsecure portion of the first memory unit when the GPU is in the unsecure mode, and configured to allow the GPU to write data only to a secure portion of the first memory unit when the GPU is in the secure mode.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: QUALCOMM INCORPORATEDInventors: Colin Christopher Sharp, Sudeep Ravi Kottilingal, Thomas Edwin Frisinger, Andrew E. Gruber
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Publication number: 20140198119Abstract: In some examples, aspects of this disclosure relate to a method for rendering an image. For example, the method includes generating visibility information indicating visible primitives of the image. The method also includes rendering the image using a binning configuration, wherein the binning configuration is based on the visibility information.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Avinash Seetharamaiah, Murat Balci, Christopher Paul Frascati, Andrew E. Gruber