Abstract: A frequency multiplier is described for synthesizing frequencies. The frequency multiplier includes a phase locked loop (PLL) circuit having an oscillator to generate a number of phase signals and a phase-shifting circuit coupled to the PLL circuit to select one of the phase signals generated by the oscillator according to a defined phase sequence to be passed to a feedback loop. Also included in the frequency multiplier is a divide-by-M circuit inserted in the feedback loop which divides a frequency of the signal selected by the phase-shifting circuit to generate a feedback signal for the PLL circuit. In one embodiment, the feedback signal generated by the divide-by-M circuit serves as a control signal to enable the phase-shifting circuit.

Abstract: A method and system for extending tTR range of memory devices coupled to a memory devices is described. A first group of memory devices and a second group of memory devices are identified. The first group includes memory devices located close to a memory controller and the second group includes memory devices located a distance away from the memory controller. Commands to access memory devices in the first and second groups are sent. A command to the first group is sent with a transitional delay when the command to the first group follows a command to the second group. In response to the commands, data from the first and second groups is received.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Abstract: In order to detect performance parameter variations at different locations, local parameter detectors are located at the various local locations. One of the local locations is selected as the reference location while the other local locations are selected as destination locations. The reference location is utilized to determine a reference parameter value, while each destination location compares its local parameter value to the reference parameter value. The parameter values are current encoded and the reference parameter value is sent to the other locations for the comparisons. The comparison at the destination locations each generates a corrective signal to compensate for the difference in the parameter value between the locations. Parameter compensation is provided to reduce performance skew among the distributed locations.

Abstract: A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the second interface have varying lengths. In order to reduce undesirable effects resulting from simultaneously switching the output signals, the delay element programmably and selectably delays the output signals according to the lengths of the traces they respectively travel to the second interface. Additionally, the effect of varying lengths of interconnect on receiver timings can be accommodated by using the delay element to programmably and selectably sample data at a receiver interface.

Abstract: A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals. In one embodiment of the present invention, a pair of inverting logic gates, coupled between a power rail and a node positively offset from ground, are used to drive the current switches in a DAC stage.

Abstract: A high impedance current mode voltage scalable driver allows signals from a higher supply voltage platform to transition to lower supply platforms. The scalable driver uses a current source to provide high impedance onto a load coupled to the driver. The driving of the load by the current source is controlled by symmetrical switches which are operated by the transition of the input signal. The driver utilizes voltage scaling to allow a particular higher supply voltage platform to transition to a variety of lower supply voltage platforms.

Abstract: A method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is first initiated. After the expiration of an exit delay period, a quiet time command is routed through a queue circuit. In one embodiment the use of a bypass circuit allows the interruption of the memory pipeline with a subsequent restart of the pipeline without excessive delay. A flexible clock is delayed by the onset of the quiet time command until the subsequent quiet time event.

Abstract: A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

Abstract: In one embodiment of the present invention, a compensation driving circuit includes a code generator, an enable circuit, and a driver. The code generator generates a driver code from a compensation code according to a selector signal. The driver code corresponds to a buffer having an impedance. The enable circuit enables the driver code. The driver controls impedance of the buffer according to the driver code.

Abstract: A high impedance current mode voltage scalable driver allows signals from a higher supply voltage platform to transition to lower supply platforms. The scalable driver uses a current source to provide high impedance onto a load coupled to the driver. The driving of the load by the current source is controlled by symmetrical switches which are operated by the transition of the input signal. The driver utilizes voltage scaling to allow a particular higher supply voltage platform to transition to a variety of lower supply voltage platforms.

Abstract: A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals.

Abstract: The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Abstract: The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a memory controller, a first Rambus channel coupled to the memory controller, a memory system coupled to the first Rambus channel and a second Rambus channel coupled to the memory system. The memory system is adaptable to determine the number of time domains on the first Rambus channel and the second Rambus channel. In a further embodiment, the memory system is adaptable to levelize memory devices coupled to the first and second Rambus channels.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.

Abstract: In one embodiment of the present invention, a compensation controller includes a counter, K driving circuits, K feedback circuits, and a state machine. The counter generates a compensation code. The K driving circuits control impedances of K buffers at K pads using the compensation code. The K feedback circuits provide K comparison results for K voltage levels at the K pads. The state machine controls the counter and the K driving circuits based on the K comparison results.

Abstract: A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals. In one embodiment of the present invention, a pair of inverting logic gates, coupled between a power rail and a node positively offset from ground, are used to drive the current switches in a DAC stage.

Abstract: A current mode digital to analog converter (DAC) that can provide an output signal having reduced glitch energy over a wide range of manufacturing tolerances and operating conditions includes a cross-over voltage controller with feedback, disposed between the current switch and the input data source. In a further aspect of the present invention, circuitry operable to generate a synchronized differential pair of digital signals as input to the cross-over voltage controller is included. In a still further aspect of the present invention, load matching circuitry is coupled to the cross-over voltage controller output terminals to reduce timing differences between various stages of the DAC.