Abstract: A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.

Abstract: A first buffer impedance value is established by electronically adjusting a first impedance between a first voltage source and a first reference point until the potential at the first reference point has a predetermined relationship to a reference voltage. A second buffer impedance value is established by adjusting the impedance between a second reference point and a second voltage source, until the potential at the second reference point has a predetermined relationship with the reference voltage.

Abstract: A DAC stage having a ground offset switch driver control signal generator, provides greater linearity by preventing rail-to-rail voltage swings of the switch driver signals.

Abstract: A clock circuit includes an oscillator having a biasing node that causes the oscillator to enter a low-power state. The clock circuit also includes a kick-start circuit and a first mechanism. The kick-start circuit operates to provide an excitation to the oscillator, where the excitation enables the oscillator to start its oscillation. The first mechanism is configured to inhibit kick-start based on certain conditions, such as when the oscillator reaches a particular level capable of sustaining oscillation by itself or when the oscillator is already running.

Abstract: A method and circuit for programming an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength. The method includes coupling a test resistor between a source of the second signaling level and a mode terminal, sensing a first level at the mode terminal, and uncoupling the test resistor from the mode terminal. If the first level is between the second signaling level and a reference level, then programming the output buffer with reference to an unterminated transmission line coupled to the mode terminal. Otherwise, programming the output buffer with reference to an external resistor coupled between a source of the first signaling level and the mode terminal. The circuit includes a first counter coupled to the first comparator to produce a first value responsive to the mode flag, the mode terminal, and the reference level.

Abstract: An apparatus and method for transferring units of information between clock domains. A respective set of N units of information is loaded from an output circuit in a first clock domain into a storage circuit in a second clock domain during each cycle of the first clock domain. Each set of N units is selected by the output circuit to include (1) units of information that have previously been loaded into the storage circuit and that will not be output from the storage circuit prior to the storage circuit being loaded with a subsequent set of N units of information, and (2) a complement number of units of information that have not previously been loaded into the storage circuit.

Abstract: An apparatus and method for indicating a phase difference between a first input signal and a second input signal. A first delayed signal is generated by delaying a reference signal for a first predetermined time and a second delayed signal is generated by delaying the reference signal for a second predetermined time, the second predetermined time being longer than the first predetermined time. The leading signal of the first and second input signals is detected. If the first input signal leads the second input signal, the first delayed signal is output to represent the first input signal and a signal that lags the first delayed signal by a third predetermined time is output to represent the second input signal. If the second input signal leads the first input signal, the second delayed signal is output to represent the first input signal and a signal that leads the second delayed signal by a fourth predetermined time is output to represent the second input signal.

Abstract: A self-synchronizing method and apparatus for exiting a dynamic random access memory from a low power state is provided. The exit from the low power state is initiated. After the expiration of an exit delay period, a first quiet time is sent on a column-access pin. A second quiet time is sent on a row-access pins to reset the memory. The first quiet time and the second quiet time are not necessarily concurrent.

Abstract: A high-speed, differential pair input buffer is constructed from a conventional differential pair having a data input terminal, a reference voltage input terminal, and an output terminal. A voltage source Vsupply and its ground connection are coupled to the differential pair through a first pair of transistors. The first pair of transistors have their enable inputs coupled to the data input terminal so that they are both biased "on" during a transition in a logic signal delivered to the data input terminal. The output terminal of the differential pair is connected through a delay circuit to the enable input terminals of a second pair of transistors, which also interconnect the differential pair to the voltage source V.sub.supply and system ground. Thus, the second pair of transistors provide a feedback path to enable the differential pair to conduct current longer if a load connected to the output of the differential pair slows the transition of the output of the differential pair.

Abstract: A disk drive controller which can be programmed for compatibility with a variety of disk drives having differing interface requirements. Information regarding specific characteristics of a disk drive to be installed is loaded into a register in the disk drive controller. Information such as the drives data rate, density, precompensation, physical designation, and mode of operation of a disk drive can be programmed into the register. The interface between the disk drive controller and the disk drive is then configured according to the stored information.

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for electrically representing data and control states each other. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. The serial bus elements are interconnected to each other using low cost two wire signal cable. Electrical signals are propagated between the serial bus elements in a differential manner. These circuitry and complementary logic of the serial bus elements jointly implement inference of data and control states from the states and/or durations of the propagating electrical signals.

Abstract: A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

Abstract: A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

Abstract: The invention is a delay locked loop circuit comprising a delay line with an input signal and a plurality of tap outputs, and a selector to select from a range of tap outputs. Each tap outputs a delayed copy of the input signal. The invention further comprises a comparator to compare the input signal to an ouput signal, and to output an indication of the phase difference between the signals. A detector coupled to the tap outputs detects a transition from a first predetermined signal level output by a first tap output to a second predetermined signal level output by a second tap output. The detector outputs an indication of the tap outputs between which the transition first occurs to a range determiner. The determiner determines a range of tap outputs to select from and outputs the determined range to the selector. The selector selects a tap output within the range, the selected tap output becoming the output signal.

Abstract: A method and apparatus for a chip to monitor its own activity and enter and exit a state of reduced power consumption. The present invention includes defining a predetermined state in which the chip could power down cleanly and monitoring the chip to determine when the chip is in that predetermined state. The present invention also includes a method and apparatus for putting the chip in a state of reduced power consumption state when the chip is in the predetermined state. The present invention also includes a method and apparatus for either turning off the clock generation circuitry or leaving it on during the power down state.

Abstract: A filter circuit of a phase locked loop circuitry fabricated on a single substrate provides an error voltage proportional to an amount of a phase difference of a comparison of a reference signal and a feedback signal. The filter circuit is coupled to a phase comparator of the phase looked loop circuitry for receiving the comparison of the reference and feedback signals. The filter circuit includes a first capacitor having a first end coupled to an output of the phase comparator and a second end coupled to ground for generating a first error voltage with respect to the amount of the phase difference of the comparison of the reference and feedback signals. The filter circuit also includes a resistor and capacitor circuit that has a first end coupled to the output of the phase comparator and a second end coupled to the ground for generating a second error voltage with respect to the amount of the phase difference of the comparison of the reference and feedback signals.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.

Abstract: An adjustable current source circuit of a phase locked loop (PLL) circuitry fabricated on a single substrate provides a first current that is a function of an error voltage proportional to an amount of a phase difference of a comparison of a reference signal and a feedback signal. The circuit includes a first current source coupled to receive a second current from a reference phase locked loop of the PLL circuitry for providing a first portion of the first current under control of the second current. The first portion of the first current is proportional to the second current. A second current source is coupled to receive a third current from a transconductance amplifier of the PLL circuitry for providing a second portion of the first current under control of the third current. The second portion of the first current is proportional to the third current. A third current source provides a third portion of the first current selectively proportional to one of the second and third currents.

Abstract: A dual loop phase locked loop system having a secondary loop for controlling various circuit, environmental and process variations. The secondary loop is comprised of a phase comparator, a filter, a transconductance amplifier and a one-shot, wherein the output of the one-shot is fed back as an input signal for comparison with a reference signal at the input of the phase comparator. The filter generates a correction voltage which is dependent on the phase difference determined by the phase comparator, and the transconductance amplifier generates a charging current corresponding to the error voltage from the filter, wherein the charging current controls the charging of the input capacitor to the one-shot circuit for determining the duration of the pulse width of the output of the one-shot. The one-shot based loop is inherently stable since there is only one pole near the origin of the S-Plane.

Abstract: An extended range logic circuit is activated to decrease the settling time and prevent slip, when phase difference of two signals being compared by a phase comparator reaches a slip point. The circuit provides error correction signals to compensate for the phase correction at a much faster rate when the phase error reaches a predetermined point, which is proximate to the slip point. However, the extended capture range circuit in only active during the lock acquisition. After lock is achieved the extended capture range logic is disabled, to provide better jitter performance.