Abstract: An oil system of a turbine engine and a method for driving an oil pump of such oil system are disclosed. In various embodiments, the oil system comprises an oil pump for fluid communication with one or more lubrication loads of the turbine engine, a first source of motive power and a coupling device. The first source of motive power is drivingly engaged to the oil pump for driving the oil pump during a first mode of operation. The coupling device is configured to drivingly disengage a second source of motive power from the oil pump during the first mode of operation and drivingly engage the second source of motive power with the oil pump to drive the oil pump during a second mode of operation.

Abstract: A configurable ME MTJ XOR/XNOR gate includes an insulator separating a top and bottom FM layer, a top ME layer with a first boundary magnetism at an interface of the top ME layer and the top FM layer, a bottom ME layer with a second boundary magnetism at an interface of the bottom ME layer and the bottom FM layer, and a top electrode coupled to the top ME layer and a bottom electrode coupled to the bottom ME layer. A voltage between the top electrode and FM layer is a first input, a voltage between the bottom electrode and FM layer is a second input, and a resistance between the top and bottom FM layer is indicative of the XOR or the XNOR of the inputs. The configurable ME MTJ XOR/XNOR gate has reduced energy consumption, smaller area, faster switching times, is non-volatile, and is configurable.

Abstract: A method of evaluating at least one parameter of a first capacitor. The method couples a number of capacitors in a capacitor network to a common node, the number of capacitors comprising at least three capacitors. Further, the method first applies a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor, and it evaluates the at least one parameter in response to the first voltage range. The method second applies a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop, and it evaluates the at least one parameter in response to the second voltage range.

Abstract: An analog differential amplifier circuit, such as an operational transconductance amplifier (OTA), with input offset correction capability. First and second analog floating gate (AFG) devices each include a trim transistor connected in parallel with a series transistor in first and second input legs, respectively, of the amplifier. Floating gate electrodes in the AFG devices are differentially programmed to correct for error in the output signal in response to zero input differential voltage at its inputs. Temperature stability is attained by programming the floating gate electrodes to gate voltages above the floating gate transistors. In one embodiment, the AFG devices each include a second trim transistor sharing the same floating gate electrode; the sum of the currents conducted by the second trim transistors is added, by way of a current mirror, to the tail current applied to the first and second input legs.

Abstract: The present disclosure pertains to the use of intense, narrow-linewidth surface, chemically-switchable ultraviolet photoluminescence from radiative recombination of the two-dimensional electron liquid with photo-excited holes in complex oxide heterostructures, such as LaAlO3/SrTiO3 (LAO/STO). Such photoluminescence from the interface between the upper and lower layers can be suppressed and restored reversibly under oxidizing and reducing conditions, respectively, as induced by chemisorption and reversal of chemisorption on the exposed surface of the heterostructure's upper member. Making use of this chemically-switchable ultraviolet photoluminescence, the present disclosure provides, inter alia, systems for detection of a chemical species, methods for determining the absence or presence of a chemical species in a sample, optoelectronic devices, and methods for producing optoelectronic devices.

Abstract: A configurable ME MTJ XOR/XNOR gate includes an insulator separating a top and bottom FM layer, a top ME layer with a first boundary magnetism at an interface of the top ME layer and the top FM layer, a bottom ME layer with a second boundary magnetism at an interface of the bottom ME layer and the bottom FM layer, and a top electrode coupled to the top ME layer and a bottom electrode coupled to the bottom ME layer. A voltage between the top electrode and FM layer is a first input, a voltage between the bottom electrode and FM layer is a second input, and a resistance between the top and bottom FM layer is indicative of the XOR or the XNOR of the inputs. The configurable ME MTJ XOR/XNOR gate has reduced energy consumption, smaller area, faster switching times, is non-volatile, and is configurable.

Abstract: A magneto-electric (ME) magnetic tunnel junction (MTJ) Exclusive-OR (XOR) gate is provided. The ME MTJ XOR gate includes an insulator separating a top ferromagnetic (FM) layer and a bottom FM layer, a top ME layer on the top FM layer, and a bottom ME layer on the bottom FM layer. The ME MTJ XOR gate also includes a top electrode coupled to the top ME layer and a bottom electrode coupled to the bottom ME layer where a voltage between the top electrode and the top FM layer is a first input, a voltage between the bottom electrode and the bottom FM layer is a second input, and a resistance between the top FM layer and the bottom FM layer is indicative of the XOR of the first input and the second input. The ME MTJ XOR has reduced energy consumption, smaller area, faster switching times, and is non-volatile.

Abstract: Provided are systems that comprises an oxygen-metal catalyst, which systems can be used to perform water-splitting or other reactions. The systems can be operated in a photochemical manner.

Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

Abstract: A gas conversion apparatus (100) for converting a process gas to one or more other gases comprises: means (105) for introducing process gas into a liquid medium in a column (125); and an ultrasonic energy generator (140) arranged to generate ultrasonic energy, the apparatus (100) being configured to launch ultrasonic energy generated by the generator (140) into the liquid medium such that process gas is exposed to ultrasonic energy, the apparatus (100) being arranged to allow collection of process gas that has been exposed to ultrasonic energy. The apparatus (100) also preferably comprises a microbubble generator (120) to generate microbubbles of the process gas for exposure to the ultrasonic energy. The ultrasonic energy generator (140) may be configured to generate ultrasonic energy as a consequence of a flow of a drive gas therethrough.

Abstract: A non-volatile memory circuit includes an SRAM cell with magnetoelectric or ferroelectric structures for maintaining data within the SRAM cell even with power off. In some implementations, the magnetoelectric and ferroelectric structures can be programmed using a NOR or tristate gate coupled to an internal state of the SRAM cell. In other implementations, the magnetoelectric and ferroelectric structures can be configured as programmable resistors in the cross-coupled signal path of the SRAM inverters.

Abstract: A vertical charge ordered transistor is disclosed. A thin charge ordered layer is employed as a tunnel barrier between two electrodes. A gate-induced accumulation of charge destabilizes the charge ordered state around the circumference of the device, opening up a parallel ohmic conduction channel, which leads to an exponential increase in source-drain current. VCOT devices have the potential to exhibit very large on/off ratios, low off-state currents, and sub-threshold slopes below 60 mV/dec.

Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

Abstract: A method of evaluating at least one parameter of a first capacitor. The method couples a number of capacitors in a capacitor network to a common node, the number of capacitors comprising at least three capacitors. Further, the method first applies a first voltage range to the capacitor network for causing a first voltage drop across the first capacitor, and it evaluates the at least one parameter in response to the first voltage range. The method second applies a second voltage range to the capacitor network for causing a second voltage drop across the first capacitor, the second voltage drop greater than the first voltage drop, and it evaluates the at least one parameter in response to the second voltage range.

Abstract: Majority and minority logic can be implemented by voltage controlled switching of magneto-electric layers of magneto electric magnetic tunnel junction (ME-MTJ) devices. A ME-MTJ device includes an exchange bias-controlled switching element and a pinned ferromagnetic layer on an antiferromagnetic layer. In one case, the switching element includes a magneto electric (ME) layer on a free ferromagnetic (FM) layer, and is separated from the pinned FM layer by an insulator. To implement a majority or minority logic gate a single ME-MTJ device may be used where the device is provided with three electrodes contacting the ME layer in an overlaying relationship with the ME layer. The orientation of the pinned FM layer indicates whether the gate is a majority or a minority logic gate.

Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

Abstract: The gas turbine engine rotor can have a body having a solid-of-revolution-shaped portion centered around a rotation axis, the body defining an annular cavity centered around the rotation axis, the annular cavity penetrating into the body from an annular opening, the annular cavity extending between two opposite annular wall portions each leading to a corresponding edge of the opening; and at least one structural plate mounted to and extending between the two opposite annular wall portions and forming an interference fit therewith.

Abstract: Provided are systems that comprises an oxygen-metal catalyst, which systems can be used to perform water-splitting or other reactions. The systems can be operated in a photochemical manner.

Abstract: The present invention relates to a new polymorphic form of the compound diosgenyl ?-L-rhamnopyranosyl-(1->2)-?-D-glucopyranoside (compound I) and pharmaceutical compositions containing this polymorph

Abstract: A body bias coordinator is provided for use with a transistor employing a body region. In one example, the body bias coordinator includes a control unit configured to control the transistor and make it operable to provide a virtual supply voltage from a source voltage during activation of the transistor. The body bias coordinator also includes a connection unit coupled to the control unit and configured to connect the body region to the virtual supply voltage during activation of the transistor. In an alternative embodiment, the connection unit is further configured to connect the body region to another voltage during non-activation of the transistor.