Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract: A first arrangement including a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine based on said address if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said second interface being configured to transmit said transaction, without modification to said address, to said third arrangement.

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract: An integrated circuit is operable to execute boot loader code and a boot code from external memory. To provide security so that the CPU does not execute malicious codes, the circuit resets in a restricted mode in which only certain functional units may be connected. In the restricted mode the CPU is only able to fetch boot code from an external memory for transfer to an internal memory. A hash function operates on the fetched boot code to determine whether it is authentic and, if it is determined that the code is authentic the circuit is reset to an unrestricted mode to continue executing from the boot code now stored in the internal memory. Further security is provided by a watchdog timer function which resets the circuit if the boot code is not determined to be authentic within a threshold period of time.

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together.

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract: A system is provided in which a first circuit is protected by security features provided by a second circuit. The first circuit comprises a processor which retrieves content from a memory. Initially, the contents of the memory are authenticated using security features of the second circuit to check that the processor is accessing authenticated content. To maintain security during use, the second circuit checks that the processor is accessing content from valid regions of the memory, being those that have been authenticated, and re-checks the authenticity of the content of the valid regions of memory. The combination of checking that the processor is accessing from valid regions of the memory and authenticating the content stored in the valid regions maximizes the security of the system. If any of the checking or authentication steps fail then operation of the system is impaired. The first circuit is thus protected by security features provided by the second circuit.

Abstract: Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory.

Abstract: Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device.

Abstract: Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that has been placed into pre-fetch memory.

Abstract: The present disclosure provides systems and methods for a cache memory and a cache load circuit. The cache load circuit is capable of retrieving a portion of data from the system memory and of storing a copy of the retrieved portion of data in the cache memory. In addition, the systems and methods comprise a monitoring circuit for monitoring accesses to data in the system memory.