Patents by Inventor Andrew P. Ritenour
Andrew P. Ritenour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9093420Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.Type: GrantFiled: March 12, 2013Date of Patent: July 28, 2015Assignee: RF Micro Devices, Inc.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Publication number: 20150171112Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Inventors: Karl Raymond Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas
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Patent number: 8988097Abstract: A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.Type: GrantFiled: June 10, 2013Date of Patent: March 24, 2015Assignee: RF Micro Devices, Inc.Inventor: Andrew P. Ritenour
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Publication number: 20140054597Abstract: The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.Type: ApplicationFiled: June 5, 2013Publication date: February 27, 2014Inventors: Andrew P. Ritenour, Paul Partyka
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Publication number: 20140057372Abstract: A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.Type: ApplicationFiled: June 10, 2013Publication date: February 27, 2014Inventor: Andrew P. Ritenour
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Publication number: 20140054601Abstract: A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.Type: ApplicationFiled: August 2, 2013Publication date: February 27, 2014Applicant: RF Micro Devices, Inc.Inventor: Andrew P. Ritenour
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Publication number: 20140054604Abstract: A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.Type: ApplicationFiled: August 23, 2013Publication date: February 27, 2014Applicant: RF Micro Devices, Inc.Inventor: Andrew P. Ritenour
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Publication number: 20140054585Abstract: A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event.Type: ApplicationFiled: August 22, 2013Publication date: February 27, 2014Applicant: RF Micro Devices, Inc.Inventor: Andrew P. Ritenour
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Publication number: 20140055192Abstract: A circuit topology for limiting saturation current in power transistors is disclosed. The circuit topology includes a normally-on transistor and a normally-off transistor coupled in series. A limiter circuit is coupled between a gate of the normally-on transistor and a source of the normally-off transistor for limiting the steady-state maximum gate-to-source voltage VGS of the normally-on transistor, which in turn limits the saturation current that flows through the normally-on transistor and the normally-off transistor.Type: ApplicationFiled: June 26, 2013Publication date: February 27, 2014Inventors: Andrew P. Ritenour, Dan Schwob
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Publication number: 20140054596Abstract: A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.Type: ApplicationFiled: April 26, 2013Publication date: February 27, 2014Applicant: RF Micro Devices, Inc.Inventor: Andrew P. Ritenour
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Publication number: 20130277687Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.Type: ApplicationFiled: March 12, 2013Publication date: October 24, 2013Applicant: RF MICRO DEVICES, INC.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Publication number: 20130280877Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.Type: ApplicationFiled: March 12, 2013Publication date: October 24, 2013Applicant: RF MICRO DEVICES, INC.Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
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Patent number: 8513675Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: GrantFiled: May 21, 2012Date of Patent: August 20, 2013Assignee: Power Integrations, Inc.Inventors: David C. Sheridan, Andrew P. Ritenour
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Publication number: 20130161663Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: ApplicationFiled: February 11, 2013Publication date: June 27, 2013Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas
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Patent number: 8389381Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: June 29, 2010Date of Patent: March 5, 2013Assignee: E Ink CorporationInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 8373211Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: GrantFiled: April 19, 2011Date of Patent: February 12, 2013Assignee: E Ink CorporationInventors: Karl R. Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas
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Publication number: 20120223340Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: ApplicationFiled: May 21, 2012Publication date: September 6, 2012Applicant: SS SC IP, LLCInventors: David C. SHERIDAN, Andrew P. RITENOUR
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Patent number: 8202772Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: GrantFiled: October 1, 2010Date of Patent: June 19, 2012Assignee: SS SC IP, LLCInventors: David C. Sheridan, Andrew P. Ritenour
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Patent number: 8058655Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: GrantFiled: November 5, 2009Date of Patent: November 15, 2011Assignee: SS SC IP, LLCInventors: David C. Sheridan, Andrew P. Ritenour
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Publication number: 20110194045Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: ApplicationFiled: April 19, 2011Publication date: August 11, 2011Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas