Patents by Inventor Andrew P. Ritenour
Andrew P. Ritenour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110020991Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: ApplicationFiled: October 1, 2010Publication date: January 27, 2011Applicant: SEMISOUTH LABORATORIES, INC.Inventors: David C. SHERIDAN, Andrew P. RITENOUR
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Publication number: 20100265239Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: ApplicationFiled: June 29, 2010Publication date: October 21, 2010Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7785988Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: October 1, 2008Date of Patent: August 31, 2010Assignee: E Ink CorporationInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Publication number: 20100148186Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.Type: ApplicationFiled: November 5, 2009Publication date: June 17, 2010Applicant: SEMISOUTH LABORATORIES, INC.Inventors: David C. Sheridan, Andrew P. Ritenour
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Publication number: 20090315044Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: ApplicationFiled: September 2, 2009Publication date: December 24, 2009Applicant: E Ink CorporationInventors: Karl R. Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas
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Patent number: 7605799Abstract: A thin-film transistor includes a gate electrode having first and second gate electrode edges on opposed sides, and a drain electrode having a first edge that overlaps the first gate electrode edge, and a second edge that overlaps the second gate electrode edge. A diode array is fabricated by successive deposition of a conductive layer, a doped semiconductor layer and an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts using a source line and a balance line.Type: GrantFiled: July 31, 2006Date of Patent: October 20, 2009Assignee: E Ink CorporationInventors: Karl R. Amundson, Yu Chen, Kevin L. Denis, Paul S. Drzaic, Peter T. Kazlas, Andrew P. Ritenour
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Patent number: 7598173Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: GrantFiled: November 16, 2006Date of Patent: October 6, 2009Assignee: E Ink CorporationInventors: Andrew P. Ritenour, Gregg M. Duthaler
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Publication number: 20090029527Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: ApplicationFiled: October 1, 2008Publication date: January 29, 2009Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7442587Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: June 15, 2006Date of Patent: October 28, 2008Assignee: E Ink CorporationInventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7223672Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: GrantFiled: April 24, 2003Date of Patent: May 29, 2007Assignee: E Ink CorporationInventors: Peter T. Kazlas, Nathan R. Kane, Andrew P. Ritenour
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Patent number: 7190008Abstract: An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear devices (102), an electro-optic medium (110) and a common electrode (112) on the opposed side of the electro-optic medium (110) from the pixel electrodes (106). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (102).Type: GrantFiled: October 27, 2004Date of Patent: March 13, 2007Assignee: E Ink CorporationInventors: Karl R. Amundson, Andrew P. Ritenour, Gregg M. Duthaler, Paul S. Drzaic, Yu Chen, Peter T. Kazlas
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Patent number: 7116318Abstract: A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.Type: GrantFiled: April 24, 2003Date of Patent: October 3, 2006Assignee: E Ink CorporationInventors: Karl R. Amundson, Yu Chen, Kevin L. Denis, Paul S. Drzaic, Peter T. Kazlas, Andrew P. Ritenour
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Publication number: 20040014265Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.Type: ApplicationFiled: April 24, 2003Publication date: January 22, 2004Applicant: E INK CORPORATIONInventors: Peter T. Kazlas, Karl R. Amundson, Yu Chen, Guy M. Danner, Kevin L. Denis, Gregg M. Duthaler, Nathan R. Kane, Andrew P. Ritenour
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Publication number: 20030222315Abstract: A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line.Type: ApplicationFiled: April 24, 2003Publication date: December 4, 2003Applicant: E INK CORPORATIONInventors: Karl R. Amundson, Yu Chen, Kevin L. Denis, Paul S. Drzaic, Peter T. Kazlas, Andrew P. Ritenour
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Patent number: 6346446Abstract: Self-aligned features of double sided integrated circuits are formed by modifying a buried layer in an integrated circuit substrate to provide a modified buried layer. The modified buried layer can be formed using ion implantation. In particular, a first feature on an upper surface of the integrated circuit is used as a mask during an ion implantation step. The first feature on the upper surface shields an underlying portion of the modified buried layer from the ion implantation, thereby preventing the modification of the underlying portion. The integrated circuit is flipped over and a lower surface of the integrated circuit is processed wherein a second feature is formed on the lower surface using the modified buried layer as a mask. Accordingly, the second feature is formed self-aligned to the modified buried layer and to the first feature.Type: GrantFiled: May 24, 1999Date of Patent: February 12, 2002Assignee: Massachusetts Institute of TechnologyInventor: Andrew P. Ritenour