Abstract: A partial HDMI physical layer (“phy”) decoder core is used in an audiovisual (A/V) sink device to perform HDCP pre-authentication on inactive HDMI ports, so as to enable fast switching between HDMI ports. Whenever a source device is connected to the any HDMI port of the A/V sink device, HDCP authentication is performed on that port immediately, even if A/V data on that port is not being output to a user. As a result, when the user switches between HDMI channels, the output is available to the user instantly, without any HDCP-related delay. The A/V sink includes the partial HDMI phy decoder core in addition to a full HDMI phy decoder core. The full HDMI phy decoder core is used to extract and decode signals received on the active port. The partial HDMI phy decoder core is used to extract and decode only those HDMI signals received on an inactive port that are needed for pre-authenticating the inactive port.

Abstract: A method and apparatus are provided for serial advanced technology attachment (SATA) hot unplug. In one embodiment, a method includes detecting a connection of a SATA storage device to a SATA host interface by monitoring physical (PHY) layer signals derived from SATA communication terminals, by a controller of the host interface. The detection being based on phase locked loop (PLL) response of the PHY layer signals. The method further includes detecting disconnection of the SATA device based on the PLL response and outputting a notification, by the controller, when the PLL response indicates that the SATA device has been disconnected.

Abstract: A method and apparatus are provided for serial advanced technology attachment (SATA) hot unplug. In one embodiment, a method includes detecting a connection of a SATA storage device to a SATA host interface by monitoring physical (PHY) layer signals derived from SATA communication terminals, by a controller of the host interface. The detection being based on phase locked loop (PLL) response of the PHY layer signals. The method further includes detecting disconnection of the SATA device based on the PLL response and outputting a notification, by the controller, when the PLL response indicates that the SATA device has been disconnected.

Abstract: A method and apparatus for calibrating the slice level of a pulse detector monitors the quality of the detected pulse signal to determine and optimize slice level. The method practiced may include two parts, including a coarse stage and a fine stage. The method practiced may further include a continuous adjustment mode of operation.

Abstract: The invention relates to antibody molecules having specificity for antigenic determinants of IL-6, therapeutic uses of the antibody molecules and methods for producing said antibody molecules.

Abstract: There is disclosed antibody molecules containing at least one CDR derived from a mouse monoclonal antibody having specificity for human CD22. There is also disclosed a CDR grafted antibody wherein at least one of the CDRs is a modified CDR. Further disclosed are DNA sequences encoding the chains of the antibody molecules, vectors, transformed host cells and uses of the antibody molecules in the treatment of diseases mediated by cells expressing CD22.

Abstract: Abstract of the Disclosure A method and apparatus for calibrating the slice level of a pulse detector monitors the quality of the detected pulse signal to determine and optimize slice level. The method practiced may include two parts, including a coarse stage and a fine stage. The method practiced may further include a continuous adjustment mode of operation.

Abstract: There is disclosed antibody molecules containing at least one CDR derived from a mouse monoclonal antibody having specificity for human TNF?. There is also disclosed a CDR grafted antibody wherein at least one of the CDRs is a hybrid CDR. Further disclosed are DNA sequences encoding the chains of the antibody molecules, vectors, transformed host cells and uses of the antibody molecules in the treatment of diseases mediated by TNF?.

Abstract: The invention relates to an antibody molecule having specificity for antigenic determinants of IL-1?, the uses of the antibody molecule and methods for producing said antibody molecule.

Abstract: The present invention relates to a method of production of antibodies wherein the heavy and light chains of a particular antibody molecule are encoded by the DNA present in a dicistronic message in which the two cistrons are linked by an optimised intergenic sequence.

Abstract: There are disclosed antibody molecules containing at least one CDR derived from a mouse monoclonal antibody having specificity for human KDR. There is also disclosed a CDR grafted antibody wherein at least one of the CDRs is a hybrid CDR. Further disclosed are DNA sequences encoding the chains of the antibody molecules, vectors, transformed host cells and uses of the antibody molecules in the treatment of diseases in which VEGF and/or KDR are implicated.

Abstract: An on-chip data independent method and apparatus for channel error estimation in a data recovery scheme is based on measuring phase noise statistics. The apparatus (10) receives a data pulse and four quadrature clock signals and has a discriminating device (11) to provide a count signal for each data pulse received depending on which clock signal was the first to clock the particular data pulse. A pair of counters (12 and 13) counts the number of data pulses received at different phase offsets to provide a value representing a statistical ratio of the counts at different clock phase offsets from which an error rate for the received data pulses based on the counts at different clock phase offsets can be determined from a look-up table (16). By re-configuring the circuitry, the system can be adapted to measure clock window asymmetry.

Abstract: An apparatus generally having a threshold slicer, a state logic device and a converter. The threshold slicer may be configured to generate a (i) first signal having an initial state of a plurality of states in response to a preceding value and a present value from an input signal and (ii) a second signal having a plurality of levels in response to the preceding value and the present value. The state logic device may be configured to generate a third signal having a sequence of the plurality of states starting with the initial state in response to the first signal. The converter may be configured to generate an output signal having the plurality of levels in response to the plurality of states in the third signal.

Abstract: An input signal is received on a digital line 10 connected to the input of a threshold slicer 60. The threshold slicer 60 provides on an output line 65 a sliced value, as is conventional, which is thereby provided to a first input of the switch 62. The threshold slicer 60 also provides a digital signal on a digital line 66 which identifies the starting state of a state machine. The starting state is determined by observing the sliced valves for two successive slicer levels which correspond to a valid succession of slicer levels, and is passed to a state logic device 63. The state logic device 63 initiates itself using the starting state received and thereafter cycles sequentially through logic states 1 to 8, corresponding to valid successions of slicer levels, with the frequency of the sampling clock. A digital value in the range 1 to 8 corresponding to the current state present in the device 63 is provided on an output line 68.

Abstract: An on-chip data independent method and apparatus for channel error estimation in a data recovery scheme is based on measuring phase noise statistics. The apparatus (10) receives a data pulse and four quadrature clock signals and has a discriminating device (11) to provide a count signal for each data pulse received depending on which clock signal was the first to clock the particular data pulse. A pair of counters (12 and 13) counts the number of data pulses received at different phase offsets to provide a value representing a statistical ratio of the counts at different clock phase offsets from which an error rate for the received data pulses based on the counts at different clock phase offsets can be determined from a look-up table (16). By re-configuring the circuitry, the system can be adapted to measure clock window asymmetry.

Abstract: A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG. 1, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line 10. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs 23 to 26. A subtracter 32 determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter 28 and a delay register 29 operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point.

Abstract: A phase detector determines an error value dependent on the relative phase between a local oscillator signal, used as the system clock, and an input signal received over a PR (a, b, a) channel. The phase error value is used to control a phase locked loop (FIG. 1, not shown). The received signal is sampled at regular intervals dependent on the local oscillator signal. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled value to three thresholds provided on respective ones of slicer threshold inputs 23, 24 and 25. A subtracter 27 determines a difference value corresponding to a difference between the ideal sample value and the actual sample value for that sampling point. A delay register 28 and a subtracter 29 operate to determine the sense of change to the current ideal sample value from an ideal sample value for a preceding sample point.

Abstract: A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal.