DATA SLICERS

Abstract

An input signal is received on a digital line 10 connected to the input of a threshold slicer 60. The threshold slicer 60 provides on an output line 65 a sliced value, as is conventional, which is thereby provided to a first input of the switch 62. The threshold slicer 60 also provides a digital signal on a digital line 66 which identifies the starting state of a state machine. The starting state is determined by observing the sliced valves for two successive slicer levels which correspond to a valid succession of slicer levels, and is passed to a state logic device 63. The state logic device 63 initiates itself using the starting state received and thereafter cycles sequentially through logic states 1 to 8, corresponding to valid successions of slicer levels, with the frequency of the sampling clock. A digital value in the range 1 to 8 corresponding to the current state present in the device 63 is provided on an output line 68. The signal provided on an output line 69 of the switch 61 is, when the line 67 is at a logical 1, that provided on the output line 68 of the state logic device 63. In this way, a state to slice converter 64 is provided, after the initial state determination, with a value corresponding to the current state of the state logic device 63, and provides on its output line 70 a slice value which corresponds to a slicer level corresponding to the current state of the state logic device 63. A switch 62, after the starting state determination, provides on an output line 27 the signal received on the line 70. In this case the output of the data slicer 22 is determined by the state logic device 63.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to data slicers.

[0002] A phase detector described in this application is the subject of UK Patent Application No. 9800353.6.

BACKGROUND OF THE INVENTION

[0003] To recover data from noisy channels, such as for example magnetic data carriers having high data densities, it is known to class the write/read channel of the data carrier in accordance with a partial response characteristic which approximates to the frequency response characteristics of the channel, and select the arrangement or design of a digital data recovery circuit to optimise data recovery from a channel with that partial response characteristic. As the correct recovery of data is so dependent on how well the channel characteristics are matched by the form of data recovery circuit selected, it is common to provide an equaliser circuit on the input of the data recovery circuit to compensate for any difference between the actual and the approximated channel characteristics.

[0004] The data recovery circuit contains a phase-lock loop circuit arrangement which receives an analogue read signal, from the equaliser circuit if there is one, and operates to control an oscillator at the phase and an integer multiple frequency of components of interest of the incoming data stream. Signals generated by this oscillator are used to sample the incoming analogue signal at appropriate sampling points, from which samples data recovery is performed. Correct phase alignment of the oscillator signals and the components of interest of the analogue read signal are critical in performing correct data recovery.

[0005] To assist the phase lock loop circuit arrangement in achieving fast initial frequency and phase alignment, the data carrier will usually have one or more regions in which VFO field data has been intentionally written. The VFO field data is a regular data pattern which, when being read, provides an analogue signal which in approximately sinusoidal and periodic in nature. In using these data channels, it is known for the data to be encoded to contain a minimum of two consecutive like bits in the data stream, and the VFO field data may for example comprise a succession of pairs of like data bits.

[0006] It is widely appreciated that certain types of optical data carrier channels currently being investigated for development will have a response characteristic approximating that of equation (1).

F(D)=a+bD+bD2+aD3  Eqn. (1)

[0007] Here, a and b are constant coefficients and D is a unit delay operator. This type of channel can be referred to as a class of partial response PR(a, b, b, a) channel.

SUMMARY OF THE INVENTION

[0008] In accordance with the present invention, a data slicer comprises means to use knowledge of the value of an input signal received on at least one clock cycle preceding a current clock cycle to estimate where in the period of a read signal a present sample value relates to, and means to provide an output signal using extrapolation of the preceding values.

[0009] In accordance with a second aspect of the present invention, a data slicer comprises:

[0010] ideal signal level determining means for determining an ideal signal level which most closely corresponds to the signal level of an input signal at a sampling point;

[0011] state means for providing a plurality of states each state corresponding to a sampling point in the period of the input signal and each state having associated therewith an ideal signal level;

[0012] state determining means for determining the initial state of said state means in response to the determined ideal signal level, and means thereafter to step said state means sequentially through said plurality of states at the sampling rate, the ideal signal level corresponding to the current state being provided as an output signal.

[0013] Preferably the state determining means determines the initial state in response also to an ideal signal level determined for a preceding sampling point.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] An embodiment of the present invention will now be described with reference to the accompanying drawings of which;

[0015] FIG. 1 shows a digital phase-lock loop in which a data slicer in accordance with the present invention can be incorporated;

[0016] FIG. 2 shows an analogue VFO field data read signal and ideal sampling points thereof;

[0017] FIG. 3 shows the phase detector of the FIG. 1 phase-lock loop; and

[0018] FIG. 4 shows a data slicer in accordance with the present invention, forming part of the phase detector of FIG. 3.

[0019] Referring to FIG. 1, the digital phase lock loop comprises a flash analogue to digital convertor (ADC) 4, a digital phase detector 5, a digital loop filter 6 and a variable frequency oscillator (VFO) 7.

[0020] The ADC 4 receives an analogue read signal on an input terminal 8 and provides a digital value Yn, representative of the amplitude of the read signal at the rising, edge of a clock signal received on a clock input terminal 9, to the phase detector 5 on a first digital line 10. The phase detector provides a phase error value &Dgr;&tgr;n, representative of a calculated difference between the actual phase of the clock signal and a desired phase, to the digital loop filter 6 on a second digital line 11. The digital filter 6 operates on the phase error value &Dgr;&tgr;n to provide a filtered phase error value to a digital to analogue converter 7A on the input of the VFO 7 on a third digital line 12. The frequency response of the filter 6 may be varied by application of different filter coefficients to coefficient input terminals 13 and 14. The VFO 7 provides a limited signal, having a phase and a frequency dependent on the signal received on the third digital line 12, on a clock line 15 to the clock input terminal 9 of the ADC 4.

[0021] Referring now to FIG. 2, the VFO field data read signal 20 is shown having an approximately sinusoidal shape of amplitude X Volts and period 2&pgr;t seconds. First to eighth ideal sampling points A to H correspond to quarters of &pgr;t from 0 to 7&pgr;/4 as shown, thus forming eight sampling points at regular intervals in the period of the signal 20.

[0022] When phase-locking and frequency-locking to the VFO field data read signal, the phase detector 5 of the present invention is set into an “acquisition” mode, in which the phase detector 5 performs the computations of Equations (2) and (3) to determine the sense of change of the amplitude of the input signal to the amplitude of the input signal at the sampling times t=n and t=n−1 respectively.

grad1=sign (Xn−Xn−1)  Eqn (2)

grad2=sign (Xn−1−Xn−2)  Eqn (3)

[0023] where: Xn is an ideal sample value at a time t=n;

[0024] Xn−1 is an ideal sample value at the preceding sample time, t=n−1; and

[0025] Xn−2 is the ideal sample value at the twice preceding sample time, t=n−2.

[0026] Following this computation, grad1 is +1 if Xn>Xn−1; −1 if Xn<Xn−1 and 0 if Xn=Xn−1. Grad2 is similarly derived.

[0027] From the results of the computations of equations (2) and (3), a value for grad is derived from the calculation shown in equation (4). 1 grad =   ⁢ grad1   ⁢ if ⁢   ⁢ grad1 = grad2   ⁢ 0   ⁢ otherwise Eqn .   ⁢ ( 4 )

[0028] When grad is not equal to zero, the computation of equation (5) is performed.

&Dgr;&tgr;n=grad (Yn−1−Xn−1)  Eqn (5)

[0029] where: &Dgr;&tgr;n is a phase error value at time t=n,

[0030] Yn−1 is a sample value at time t=n−1, and

[0031] Xn−1 is the ideal sample value at time t=n−1.

[0032] When grad is equal to zero, the phase detector 5 determines the phase error value as in Equation (6).

&Dgr;&tgr;n=&Dgr;&tgr;n−1  Eqn. (6)

[0033] The result of these calculations is that for all sample points where the gradient of the read signal 20 is the same for two successive sample intervals, i.e. sample points A, B, C, E, F and G, the phase error value is proportional to the difference between the actual sample value and the ideal sample value at time t=n−1. It will be noted that a new phase error value &Dgr;&tgr;n is thus calculated six times in the period of the VFO field data read signal 20.

[0034] The phase detector 5 is shown in detail in FIG. 3, in which the first digital line 10 and the second digital line 11 are six bit digital lines, thus allowing each of Yn and &Dgr;&tgr;n to assume a decimal value in the range of −32 to +31.

[0035] The value of Yn on the digital line 10 is examined by a data slicer 22, which then determines the ideal sample value. In a conventional data slicer, this determination is made by digitally comparing Yn to four thresholds provided on respective ones of slicer threshold inputs 23, 24, 25 and 26. The threshold provided on the input 23 corresponds to the mean value of L0 and L1, the threshold on the input 24 corresponds to the mean value of L1 and L2, the threshold provided on the input 25 corresponds to the mean value of L2 and L3, and the threshold provided on the input 26 corresponds to the mean value of L3 and L4. By examining which of the thresholds are exceeded by Yn, the conventional data slicer 22 determines which of the levels L0, L1, L2, L3 and L4 Yn is most similar to in value, and provides the value so determined on a further digital line 27 as Xn.

[0036] In accordance with the present invention, the data slicer 22 uses knowledge of the value of Yn received on preceding clock cycles to estimate where in the period of the read signal 20 the present sample value relates to, and determine Xn using extrapolation of preceding values of Yn and examination of the current value of Yn. This alternative provides a phase detector 5 which is less likely to determine an incorrect value of Xn in the face of a noisy read signal 20 than the conventional data slicer arrangement described above.

[0037] In FIG. 4, the data slicer 22 is shown, comprising a threshold slicer 60, first and second digital switches 61, 62, a state logic device 63 and a state to slice converter device 64.

[0038] The digital line 10 is connected to the input of the threshold slicer 60 which provides, on an output line 65, a sliced value, which is thereby provided to a first input of the switch 62. The threshold slicer 60, in providing the sliced value on the digital line 65, thus operates in the same way as the conventional data slicer described above by determining the signal level L0 to L4 which most closely corresponds to the level of the input signal. The threshold slicer 60 further includes logic arranged to provide a digital signal on a digital line 66 which identifies the starting state of a state machine. The starting state is determined by observing the sliced valves for two successive slicer levels which correspond to a valid succession of slicer levels. Whereas the sliced value provided on the line 65 may be any one of the levels L0 to L4, the value provided on the line 66 falls within the range of 1 to 8, that is it identifies the starting state of the state machine based on the first two initial valid threshold states.

[0039] To implement the data slicer components 61, 63 and 64, the threshold slicer provides a logic 1 signal on a further line 67. The line 67 is connected to the switching inputs of each of the digital switches 61 and 62. In this way, each of the switches 61, 62 is controlled to pass through to its output the signal which is present on its opposite input, i.e. the input shown lowermost in FIG. 4. However, before signals provided by the data slicer components 61, 63 and 64 can be provided on the line 27, the line 67 must be provided with a logical 0 signal for a minimum of two samples before it is switched to allow the threshold slicer 60 to determine the (approximate) phase of the signal received on the line 10.

[0040] The state logic device 63 contains logic which is able to cycle through states 1 to 8, corresponding to levels L2-L3-L4-L3-L2-L1-L0-L1 respectively, with the sampling clock at the sampling frequency. The state logic device 63 receives the starting state, determined by logic in the threshold slicer 60, from the digital line 66. The state logic device 63 initiates itself using the starting state so received and thereafter cycles sequentially through the states with the frequency of the sampling clock. The state logic device provides on its output line 68 a digital value in the range 1 to 8 corresponding to the current state present in the device 63.

[0041] The signal provided on an output line 69 of the switch 61 is, when the line 67 is at a logical 1, that provided on the output line 68 of the state logic device 63. In this way, the state to slice converter 64 is provided, after the initial state determination, with a value corresponding to the current state of the state logic device 63. The state to slice converter 64 provides on its output line 70 a slice value corresponding to the level L0 to L4 which corresponds to the current state provided by the state logic device 63. As the switch 62, after the initial state determination, provides on the output line 27 the signal received on the line 70, the output of the data slicer 22 is determined by the state logic device 63 and the sampling clock and is thus not susceptible to slicing errors occurring in the threshold slicer 60. The present data slicer is thus less susceptible to cycle stealing or slipping than the conventional data slicer described above.

[0042] The digital line 27 carries the value of Xn provided by the data slicer 22 to a subtracter device 28 and to a delay register 29. The delay register 29 provides the value provided by the data slicer 22 on the preceding clock cycle, i.e. Xn−1, on a further digital line 30 to a further delay register 31, to a second subtracter 32 and to a third subtracter 33.

[0043] The subtracter device 32 digitally subtracts Xn−1, received on the line 30, from Yn−1 derived from Xn on the line 10 by a further delay register 34 and provided thereby on a further digital line 35, and provides a difference value Yn−1−Xn−1 corresponding to the difference between these values on a further digital line 36. A digital switch 37 receives both the difference value from the subtracter device 32 and the inverse of the difference value from an inverter device 38. The inverter device 38, in effect, inverts the sign of the value of Yn−1−Xn−1 on a branch 39 of the line 36 and provides the result to the digital switch 37 on a line 40.

[0044] The delay register 31 provides on a further digital line 41 the value of Xn on the twice preceding clock cycle, i.e. Xn−2, which is then subtracted from the value of Xn−1 by a further subtracter 42. The sign of the result of this subtraction, which is the calculation of Equation (3), is thus representative of the sense of change to the preceding ideal sample value from the twice preceding sample value. This sign, when positive, is provided as a logical 1 signal on an output line 43 to a switch control input of the digital switch 37 and to an input of an EXOR gate 48. Thus, a positive result from the Equation (3) calculation causes the Yn−1−Xn−1 value from the line 36 to be provided on a further digital line 44, and a negative result from the Equation (3) calculation causes the inverse value from the line 40 to be provided on the line 44. The switch 37 thus performs the calculation of Equation (5), operating on the difference value in dependence on the sense of change to the preceding ideal sample value from the twice preceding sample value. Where the subtraction of Xn−2 from Xn−1 results in zero, i.e. there is no sign, a logical 1 signal is provided on an output line 45 to an input of an OR gate 46.

[0045] The subtracter 28, functionally similarly to the subtracter 42, provides a logical 1 signal on an output line 47 to an input of the OR gate 46 if the subtraction of Xn−1 from Xn results in zero. The sign of the result of this subtraction, which is the result of the calculation of equation (2), is thus representative of the sense of change to the ideal sample value from the preceding ideal sample value. This sign, when positive, is provided as a logical 1 signal to an input of the EXOR gate 48 on a line 49, and is provided as a logical 0 signal on the line 49 otherwise.

[0046] The effect of the OR gate 46 and the EXOR gate 48, which has its output connected to a further input of the OR gate 46, is to provide a logical 1 signal on an output line 50 of the OR gate 46 when any of the following conditions are satisfied: the result of equation (2) is zero; the result of equation (3) is zero; or one but not the other of equations (2) and (3) has a positive result. The arrangement 46, 48 thus determines when both of the senses of change are the same and are non-zero.

[0047] The output line 50 of the OR gate 46 is connected to the switch control input of a further digital switch 51. The value on the digital line 44, which is the result of the Equation (5) calculation, is passed as &Dgr;&tgr;n onto the output digital line 11 of the switch 51 when a logical 0 signal is present on the line 50. When the signal provided by the OR gate 46 on the line 50 a logical 1, the switch 51 is caused to pass as &Dgr;&tgr;n onto the line 11 a value provided by a feedback circuit comprising a further delay register 52, a divide by two device 53 and a further digital switch 54. The delay register 52 receives the value of &Dgr;&tgr;n from the digital line 11 and provides the value of &Dgr;&tgr;n on the preceding clock cycle; i.e. &Dgr;&tgr;n−1, on a further digital line 55 to both of an input of the switch 54 and an input of the divide by two device 53. The divide by two device 53 provides one half of the &Dgr;&tgr;n value to a second input of the switch 54 on a further digital line 56.

[0048] Whether the switch 54 passes the value from the divide by two device 53 or the value from the delay register 52 to the second input of the switch 51 on a further digital line 57 depends on the logic signal applied to the control switch input of the switch 54. Preferably a mode device (not shown) provides a logical 1 signal to the switch control input of the switch 54, thereby providing the output value of the delay register 52 to the switch 51, when the phase-lock loop of FIG. 1 is in acquisition mode, and provides a logical 0 signal to the switch control input of the switch 54 when in a track mode.

[0049] In this way, because the value of &Dgr;&tgr;n is held from the preceding clock cycle when either of equations (2) and (3) result in zero or one but not the other has a positive result, rapid lock can be achieved when reading VFO field data. When in a track mode, the holding of the value of &Dgr;&tgr;n from the preceding clock cycle could cause the phase-lock loop to become unlocked when the read signal contains a significant number of consecutive like bits. To avoid this situation, the mode device (not shown) switches the digital switch 51 to receive values from the divide by two device 53. In this way, the “valid” value of &Dgr;&tgr;n, i.e. the previous term calculated from a sample value where the OR gate 46 provided a logical 0 output signal, is successively divided by two for every sample time instance, until the value of &Dgr;&tgr;n eventually dwindles to zero, or a “valid” value of &Dgr;&tgr;n occurs.

Claims

1. A data slicer comprising means to use knowledge of the value of an input signal received on at least one clock cycle preceding a current clock cycle to estimate where in the period of a read signal a present sample value relates to, and means to provide an output signal using extrapolation of the preceding values.

2. A data slicer in accordance with claim 1 in which the state determining means determines the initial state in response also to an ideal signal level determined for a preceding sampling point.

3. A data slicer comprising:

ideal signal level determining means for determining an ideal signal level which most closely corresponds to the signal level of an input signal at a sampling point;

state means for providing a plurality of states each state corresponding to a sampling point in the period of the input signal and each state having associated therewith an ideal signal level;

state determining means for determining the initial state of said state means in response to the determined ideal signal level, and means thereafter to step said state means sequentially through said plurality of states at the sampling rate, the ideal signal level corresponding to the current state being provided as an output signal.

4. A data slicer in accordance with claim 3 in which the state determining means determines the initial state of the state means in response to an observation that the determined ideal signal levels for at least two successive ideal signal levels correspond to a valid succession of ideal signal levels.

5. A method of providing an output signal comprising:

determining an ideal signal level which most closely corresponds to the signal level of an input signal at a sampling point;

providing a plurality of states each state corresponding to a sampling point in the period of the input signal and each state having associated therewith an ideal signal level;

determining the initial state of said state means in response to the determined ideal signal level,

stepping sequentially through said plurality of states at the sampling rate, and

providing as an output signal the ideal signal level corresponding to the current state.

6. A method in accordance with claim 5 in which the initial state is determined by observing that the determined ideal signal levels for at least two successive ideal signal level correspond to a valid succession of ideal signal levels.