Patents by Inventor Andrew W. Vogan

Andrew W. Vogan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8990614
    Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Patent number: 8949512
    Abstract: Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Andrew W. Vogan, Matthew J. Byom, Daniel J. Post
  • Patent number: 8935459
    Abstract: Systems and methods are disclosed for heuristics associated with programming data in a non-volatile memory (“NVM”). One or more applications can generate information that notifies a system of the amounts of recoverable and unrecoverable new data that will be programmed to an NVM. Based on this information, the system can calculate the amount of new data that needs to be placed in a bulk mode instead of a SLC mode. By utilizing multi-modal modes of an NVM effectively, the system can improve overall performance and reduce the probability of unnecessary garbage collection.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 13, 2015
    Assignee: Apple Inc.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Publication number: 20140281050
    Abstract: In one embodiment, a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile electrically erasable semiconductor memory comprises one or more banks of electrically erasable semiconductor memory coupled to a storage processor. The storage processor can processes access requests for the memory, and has components including: a command interface, an expectation table, and a mode selector. The command interface receives memory access requests, which include a tag to identify the request, and an external priority associated with the request. The expectation table includes a set of times associated with each of the external priority levels, which indicate the period in which a request having the external priority is expected. The mode selector selects from a set of storage processor operation modes including a standard mode and a preemption mode.
    Type: Application
    Filed: August 12, 2013
    Publication date: September 18, 2014
    Applicant: Apple Inc.
    Inventor: Andrew W. Vogan
  • Publication number: 20140281588
    Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Apple Inc.
    Inventors: Andrew W. Vogan, Matthew J. Byom, Alexander C. Sanks, Daniel J. Post, Hari Hara Kumar Maharaj, Nir Jacob Wakrat, Kenneth L. Herman
  • Publication number: 20140281687
    Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: APPLE INC.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Publication number: 20140281814
    Abstract: Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: APPLE INC.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Patent number: 8705281
    Abstract: A method and system to facilitate the usage of memory modules that have one or more defective memory dies. In one embodiment of the invention, a memory module is packaged with a number of dies and the memory module is tested and sorted according to the number of dies that pass testing. Each signal of each die in the memory module has an unique bond-out or connection point in the package of the memory module. By separating the signals of each die in the memory module, any defective die can be easily isolated and this allows a significant cost reduction in products that use a large number of dies.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventor: Andrew W. Vogan
  • Patent number: 8621141
    Abstract: A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 31, 2013
    Assignee: Intel Corporations
    Inventors: Eric D. Mudama, David M. Jones, Andrew W. Vogan
  • Publication number: 20130326113
    Abstract: Systems and methods are disclosed for usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory (“NVM”). In some embodiments, a host of the system can issue queue-able trim commands by dispatching non-data transfer write commands to the NVM. In some embodiments, the host can track the read behavior of a particular application over a period of time. As a result, the host can maintain heuristics of logical sectors that are most frequently read together. The host can then notify the NVM to pre-fetch data that the application will most likely request at some point in the future. These notifications can take the form of non-data transfer read commands. Each non-data transfer read commands can include a flag bit that is set to indicate that no data transfer is desired.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: APPLE INC.
    Inventors: Nir Jacob Wakrat, Andrew W. Vogan
  • Publication number: 20130238833
    Abstract: Systems and methods are disclosed for heuristics associated with programming data in a non-volatile memory (“NVM”). One or more applications can generate information that notifies a system of the amounts of recoverable and unrecoverable new data that will be programmed to an NVM. Based on this information, the system can calculate the amount of new data that needs to be placed in a bulk mode instead of a SLC mode. By utilizing multi-modal modes of an NVM effectively, the system can improve overall performance and reduce the probability of unnecessary garbage collection.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: APPLE INC.
    Inventors: Andrew W. Vogan, Daniel J. Post
  • Publication number: 20130219106
    Abstract: Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: APPLE INC.
    Inventors: Andrew W. Vogan, Matthew J. Byom, Daniel J. Post
  • Publication number: 20110246705
    Abstract: A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 6, 2011
    Inventors: Eric D. Mudama, David M. Jones, Andrew W. Vogan
  • Publication number: 20110242894
    Abstract: A method and system to facilitate the usage of memory modules that have one or more defective memory dies. In one embodiment of the invention, a memory module is packaged with a number of dies and the memory module is tested and sorted according to the number of dies that pass testing. Each signal of each die in the memory module has an unique bond-out or connection point in the package of the memory module. By separating the signals of each die in the memory module, any defective die can be easily isolated and this allows a significant cost reduction in products that use a large number of dies.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Inventor: ANDREW W. VOGAN
  • Patent number: 8019925
    Abstract: Methods and structures for mapping of logical to physical block addresses within a disk drive to provide independence of the logical block size and the physical disk block size. The independence of the logical and physical block sizes enables numerous beneficial features to improve disk drive capacity, performance and reliability. In one exemplary aspect, indirect mapping table structures and methods map an LBA to an associated IBA representing a block of the same size as the logical block. The IBA is then converted to a corresponding starting quantum unit of data identified by a QA. The QA is, in turn, converted to a disk block identified by a starting DBA and an offset within that DBA. The disk block may be of variable size and is independent of the size of the identified LBA. Numerous other features are enabled by the logical to physical mapping features hereof.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: September 13, 2011
    Assignee: Seagate Technology LLC
    Inventors: Andrew W. Vogan, Bruce Liikanen
  • Patent number: 7916421
    Abstract: Methods and structures for recovering from an off-track position error in a dynamically mapped storage device. In a dynamically mapped storage device data is dynamically mapped to a physical location on the recordable media. Thus, when a write fault occurs, such as an off-track position error, the data may be re-written and re-mapped at a different location on the recordable media. In a dynamically mapped storage device data may be reordered into a sequential stream of contiguous physical data blocks. Random host data blocks may be mapped into sequential physical data blocks on the recordable media. Further, the sequential reordering of the data blocks may ensure that no data is present in tracks or sectors directly ahead of the track of sector being written. Further, the system has the ability to store multiple revolutions of host supplied data within the disk drive memory buffer and maintain the information in memory while writing it to the recordable media.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: March 29, 2011
    Assignee: Seagate Technology LLC
    Inventors: Bruce A. Liikanen, Andrew W. Vogan
  • Patent number: 7752491
    Abstract: Methods and structures for providing on-the-fly head depopulation in a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof allow on-the-fly head depopulation to protect data when a subsection of a storage device, such as a head of surface is failing. When the storage device detects that a head is failing, data may be migrated off the failing subsection into other subsections (e.g., a different head or surface) using mapping features and aspects hereof. Thus, the data on the failing subsection is still available should the subsection or head eventually fail.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: July 6, 2010
    Assignee: Seagate Technology LLC
    Inventors: Bruce A. Liikanen, John W. VanLaanen, Andrew W. Vogan
  • Patent number: 7685360
    Abstract: Methods and structures for appending metadata with recorded data in a dynamic mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof allow presently unused physical space to be used for storing additional metadata associated with recorded data. As the current capacity ratio of the storage device increases, appending of metadata may cease and previously recorded data including metadata may be re-recorded (migrated) to eliminate the appended metadata. The appended metadata may be used for enhanced diagnosis and analysis of characteristics of the operating storage device and may be used to restore the content of the storage device to an earlier state. The metadata may include, for example, track following position of the read/write head, temperature, head flying height, and time of day.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: March 23, 2010
    Assignee: Seagate Technology LLC
    Inventors: Don Brunnett, Bruce A. Liikanen, John Mead, Eric D. Mudama, John W. VanLaanen, Andrew W. Vogan
  • Patent number: 7653847
    Abstract: Methods and structures for performing field flawscan to reduce manufacturing costs of a dynamic mapped storage device. In a dynamic mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof permit flawscan testing of a storage device to be completed substantially concurrently with processing write requests for its intended application. A fraction of the storage device may be certified by an initial flawscan performed during manufacturing testing. Statistical sampling sufficient to assure a high probability of achieving specified capacity may be performed to reduce manufacturing time and costs in testing. Final flawscan of the remainder of the storage locations may be performed substantially concurrently with processing of write requests after the device is installed for its intended application.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: January 26, 2010
    Assignee: Seagate Technology LLC
    Inventors: Bruce A. Liikanen, Eric D. Mudama, John W. VanLaanen, Andrew W. Vogan
  • Patent number: 7620772
    Abstract: Methods and structures for dynamic density control to improve reliability of a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide for dynamically altering the recording density of user data stored on the storage device. So long as the physical capacity utilization of the storage device permits, new data stored on the device may be stored at lower density to improve reliability in reading back the recorded data. Further features and aspects hereof may reduce the recording density only for data deemed to be critical. Radial (track) density, longitudinal (bit) density, or both may be dynamically controlled to reduce recording density. As physical capacity utilization increases, data previously recorded at lower density may be migrated (re-recorded) at normal higher density.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: November 17, 2009
    Assignee: Seagate Technology, LLC
    Inventors: Bruce A. Liikanen, Mike L. Mallary, John Mead, Eric D. Mudama, John W. VanLaanen, Andrew W. Vogan