Abstract: Methods and structures for writing thermal lead-in sequences to provide head stability in a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide writing thermal lead-in sequences to allow the write head to stabilize. As the write head begins writing a sequence of data to the recordable media, the write head may not have a desired thermal stability. Thus, there may be thermal flux with some of the data, affecting the reliability of the data. Mapping features and aspects hereof allow the write head to write a thermal lead-in sequence of data that does not destroy valuable data, allowing the write head to begin writing before stabilizing. Writing the thermal lead-in sequence will cause the write head to warm up and become stable, and thus be ready to write valid data.

Abstract: Methods and structures for dynamic multiple indirections to improve reliability and performance of a dynamically mapped storage devices. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide for dynamically altering the number of replicated copies (multiple mapped indirections) of user data stored on the storage device. Performance information regarding operation of the storage device may be gathered by the storage device controller such that where physical capacity of the storage device permits and as degrading reliability is detected, additional copies (multiple indirections) of stored user data may be written to the mapped storage device. Increased multiple indirections improves reliability by decreasing the probability of data loss in response to various failure modes of the storage device.

Abstract: Methods and structures for providing patches or updates to embedded ROM firmware simply and inexpensively while avoiding imposition of execution or memory fetch overhead. A patch memory includes locations storing addresses and optional alternate data values. Read/fetch operations addressed to a firmware ROM memory are applied in parallel to the patch memory. All locations of the patch memory may be compared in parallel to the supplied address to determine if a match is found in patch memory. If no match is found, the read/fetch memory cycle completes normally retrieving data from the ROM memory. If a match is found, the alternate data value is applied to the data bus in place of the ROM memory data retrieved. Any ROM location may therefore be patched regardless of whether the location stores instruction or data.