Abstract: Technologies are generally described herein for handling interrupts within a multiprocessor computing system. A priority level associated with a current task for each processor of the multiprocessor computing system can be maintained. Cache state information associated with each processor can also be maintained. Upon receiving an interrupt to the multiprocessor computing system, a cache locality score for each processor can be determined based on the maintained cache state information. A value can be computed that balances, for each processor, the priority level and the cache locality score. A processor for servicing the interrupt can be determined based on the computed value. The determined processor can be signaled to service the interrupt. Tracking state information related to processor cores can support rapid allocation of an arriving interrupt to a processor core without collecting processor core state information at interrupt time.

Abstract: A rotary surface cleaning machine for cleaning floors, including both carpeted floors and uncarpeted hard floor surfaces including but not limited to wood, tile, linoleum and natural stone flooring. The rotary surface cleaning machine has a rotary surface cleaning tool mounted on a frame and coupled for high speed rotary motion relative to the frame. The rotary surface cleaning tool has a substantially circular operational surface that performs the cleaning operation. The rotary surface cleaning tool is driven by an on-board power plant to rotate at high speed. The rotary surface cleaning tool is coupled to a supply of pressurized hot liquid solution of cleaning fluid and a powerful vacuum suction source.

Abstract: Technologies are described herein for allocating interrupts within a multiprocessor computing system. Information communicated to an interrupt controller module can support allocating interrupt response resources so as to maintain processor affinity for interrupt service routines. This affinity can support caching efficiency by executing a specific interrupt handler on a processor that previously executed that interrupt handler. The caching efficiency may be balanced against the benefits of assigning execution of the interrupt hander to another processor that is currently idle or currently processing a lower priority task.

Abstract: Health-sensing and health-action devices and systems are generally described. The health-sensing device may include one or more of a sensor, a filter, and a transmitter. The sensor may be configured to sense one or more factors relating to an indicator of a health related condition or occurrence such as snoring and may include one or more microphone devices, accelerometers, and/or MEMs devices. The filter may be configured to evaluate a signal from the sensor and determine if the indicator has been detected. The transmitter may be arranged for initiating a transmission based on a signal from the filter. The health-action device may be configured for responding to an indicator of a health related condition or occurrence of a user and may include one or more of a receiver, a processor, and a responder. The health-action device may stimulate the user or may cancel the snoring sound.

Abstract: The present disclosure generally relates to a touch-sensitive LED display device with a number of shared circuits having measurement circuitry electrically coupled to display circuitry. A processor receives signals from the measurement circuitry and may compare the signals to determine a location of the touch on the touch screen.

Abstract: Techniques are generally described related to a multi-core processor with a plurality of processor cores and a cache memory shared by at least some of the processor cores. The multi-core processor can be configured for separately allocating a respective level of cache memory associativity to each of the processing cores.

Abstract: A data storage method and system. The method includes defining, by a computing system, a meta-object, a schema based structured definition for the meta-object, and a taxonomy with configuration data. The computing system creates content associated with the taxonomy and associates topics of the content with a logical storage room representations. Reference coordinates associated with the logical storage room representations are associated with the taxonomy. The computing system generates updated configuration data that includes the reference coordinates and a uniform resource identifier associated with the content is generated. The computing system generates an account associated with the meta-object for a user. Metering charges for usage of the account and a report associated with the account and usage are generated.

Abstract: A data storage method and system. The method includes defining, by a computing system, a meta-object, a schema based structured definition for the meta-object, and a taxonomy with configuration data. The computing system creates content associated with the taxonomy and associates topics of the content with a logical storage room representations. Reference coordinates associated with the logical storage room representations are associated with the taxonomy. The computing system generates updated configuration data that includes the reference coordinates and a uniform resource identifier associated with the content is generated. The computing system generates an account associated with the meta-object for a user. Metering charges for usage of the account and a report associated with the account and usage are generated.

Abstract: The present disclosure relates to a display device with an OLED display including a plurality of nodes configured to emit light when drive circuitry provides a signal across the plurality of nodes at or above an illumination threshold. Measurement circuitry may be disposed proximate to the plurality of nodes and may be configured to sense the light reflected off of an object positioned over the OLED display to provide measurement signals. The measurement signals can be evaluated to determine the location of the display proximate to the object that provides the reflected light.

Abstract: Health-sensing and health-action devices and systems are generally described. The health-sensing device may include one or more of a sensor, a filter, and a transmitter. The sensor may be configured to sense one or more factors relating to an indicator of a health related condition or occurrence such as snoring and may include one or more microphone devices, accelerometers, and/or MEMs devices. The filter may be configured to evaluate a signal from the sensor and determine if the indicator has been detected. The transmitter may be arranged for initiating a transmission based on a signal from the filter. The health-action device may be configured for responding to an indicator of a health related condition or occurrence of a user and may include one or more of a receiver, a processor, and a responder. The health-action device may stimulate the user or may cancel the snoring sound.

Abstract: The present disclosure relates to a system for hierarchical read-combining memory having a multicore processor operably coupled to a memory controller. The memory controller is configured for receiving a plurality of requests for data from one or more processing cores of the multicore processor, selectively holding a request for data from the plurality of requests for an undetermined or indefinite amount of time, and selectively combining a plurality of requests for the same data into a single read-combined data request. The present disclosure further relates to a method for hierarchical read-combining data requests of a multicore processor and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for hierarchical read-combining data requests of a multicore processor.

Abstract: Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to at least two of the plurality of processor cores. A compiler determined map may separately allocate a memory space to threads of execution processed by the processor cores.

Abstract: A data access control method and system. The method includes receiving by a computer processor from a requestor, a request for access to data. The computer processor extracts from the request, a requestor identification string associated with the requestor. The computer processor verifies a match for the requestor identification string, a service requestor identification string, a requestor software component operating process identification string, a requestor server identification string, a requestor hardware device network address and a requestor MAC address, and a requestor hardware device identification string against a plurality of registries. The computer processor generates an access point door associated with a specified logical storage room representation comprising the data. The computer processor enables access to the data via the access point door and the specified logical storage room representation based on enabling a logical lock with a logical key and a valid timestamp.

Abstract: Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a first region of the multi-core processor configured to dynamically receive a first supply voltage and a first clock signal, a second set of processor cores in a second region of the multi-core processor configured to dynamically receive a second supply voltage and a second clock signal, and an interface block coupled to the first set of processor cores and the second set of processor cores, wherein the interface block is configured to facilitate communications between the first set of processor cores and the second set of processor cores.

Abstract: Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determined. Current task priority levels can be queried from one or more processors of the multiprocessor computing system. One of the processors can be assigned to execute the interrupt handler in response to the processor having a lowest current task priority level. Interrupt arbitration can schedule and communicate interrupt responses among processor cores in a multiprocessor computing system. Arbitration can query information about current task or thread priorities from a set of processor cores upon receiving an interrupt. The processor core that is currently idle or running the lowest priority task may be selected to service the interrupt.

Abstract: Embodiments of the disclosure generally set forth techniques for supplying different voltage levels and clock signals to a processor core. One example method includes determining a first workload of a first processor core in the multi-core processor for performing a first computing task associated with a first image area and a first geometric mapping between the first computing task and the first processor core, selecting a first voltage level or a first clock signal having a first clock frequency for the first processor core based on the determined first workload, wherein the first voltage level is compatible with the selected first clock frequency, initiating a voltage change to the first processor core based on the selected first voltage level, and initiating a clock change to the first processor core based on the selected first clock signal having the first clock frequency.

Abstract: Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to calculating a clock rate for one or more of the processor cores in the multi-core processor. One example method may include determining a first estimated workload for a first processor core and a second estimated workload for a second processor core within a scheduling interval in a periodic scheduling environment. In addition, a first clock rate for the first processor core may be calculated based on one or more of the first estimated workload, a maximum clock rate supported by the multi-core processor and/or the scheduling interval. Similarly, a second clock rate for the second processor core may also be calculated based on one or more of the second estimated workload, the maximum clock rate, and/or the scheduling interval.

Abstract: Techniques described herein generally relate to multi-core processors including two or more processor cores. Example embodiments may set forth devices, methods, and computer programs related to thermal management in the multi-core processor. Some example methods may include retrieving a first temperature reading for the first processor core during a scheduling interval, retrieving a second temperature reading for the second processor core also during the scheduling interval, and assigning a first task to the first processor core to be executed based on a comparison of the first temperature reading and the second temperature reading retrieved during the scheduling interval.

Abstract: A data access control method and system. The method includes receiving by a computer processor from a requestor, a request for access to data. The computer processor extracts from the request, a requestor identification string associated with the requestor. The computer processor verifies a match for the requestor identification string, a service requestor identification string, a requestor software component operating process identification string, a requestor server identification string, a requestor hardware device network address and a requestor MAC address, and a requestor hardware device identification string against a plurality of registries. The computer processor generates an access point door associated with a specified logical storage room representation comprising the data. The computer processor enables access to the data via the access point door and the specified logical storage room representation.

Abstract: A data storage and retrieval method and system. The method includes defining, by a computing system, a meta-object, a schema based structured definition for the meta-object, and a taxonomy with configuration data. The computing system creates content associated with the taxonomy and associates topics of the content with a logical storage room representations. Reference coordinates associated with the logical storage room representations are associated with the taxonomy. The computing system generates updated configuration data comprising the reference coordinates and a uniform resource identifier associated with the content is generated. The computing system generates an account associated with the meta-object for a user. Metering charges for usage of the account and a report associated with the account and usage are generated.