Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

Abstract: A multistage amplifier for outputting a first output signal includes: an input stage circuit, a middle stage circuit and an output stage circuit. The input stage circuit includes at least one amplifying circuit, which receives the first output signal and a reference signal, thereby to generate a second output signal at an output terminal of the input stage circuit. The middle stage circuit is used to perform frequency compensation on the multistage amplifier. The output stage circuit is used to generate the first output signal at an output terminal of the output stage circuit according to the second output signal. The output stage circuit includes at least one current limiting circuit, where the current limiting circuit is controlled by the second output signal, thereby to adjusting a voltage level of the first output signal.

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described.

Abstract: Provided herein are methods for labeling the proteomes of cells, as well as methods for labeling proteins or populations of proteins produced by cells. In some embodiments, the methods comprise introducing variant aminoacyl-tRNA synthetases and noncanonical amino acids into cells. Also provided herein are polynucleotides encoding variant aminoacyl-tRNA synthetases that recognize noncanonical amino acids. The methods and compositions provided herein are useful for, among other things, identifying target cells and identifying biomarkers of interest.

Abstract: A container storing a liquid anesthetic solution is disclosed. The container is sealed by a closure, and the liquid anesthetic solution includes an anesthetic being from 0.1% to 10% by weight of the liquid anesthetic solution, water, and a solvent. The container includes a material that is inert to the anesthetic, and the closure includes siliconized rubber, a fluoropolymer, or metal that is inert to the anesthetic. The concentration of the anesthetic in the liquid anesthetic solution stored in the container following a predetermined time period is at least 93% of a concentration of the anesthetic in the liquid anesthetic solution before the liquid anesthetic solution is stored in the container.

Abstract: A pilot signal detection and indication unit includes a pilot signal scaling unit structured to generate a scaled pilot signal by shifting a pilot signal using a bias voltage and scaling down the pilot signal, a pilot signal duty cycle comparator unit structured to generate a limited pilot signal that has a fixed peak voltage and a duty cycle that is equivalent to the duty cycle of the pilot signal, a processing unit structured to determine a voltage value and the duty cycle value of the pilot signal from the scaled pilot signal and the limited pilot signal, and to generate an indication signal based on the determined voltage value and duty cycle value, and an indication unit having a number of indicators and being structured to activate selected ones of the number of indicators based on the indication signal.

Abstract: Self-powered switches include a switch housing having an externally accessible user input member, a coil assembly, and a magnet arranged therein such that at least one of the coil assembly and the magnet move relative to each other responsive to movement of the user input member between first and second switch positions, and a control circuit held in the switch housing and coupled to first and second terminals of the coil assembly. The control circuit is configured to detect respective electrical characteristics of the first and second terminals of the coil assembly responsive to the movement of the user input member, and selectively transmit first and second wireless control signals to a remote receiver based on the respective electrical characteristics of the first and second terminals of the coil assembly, respectively. Related circuits and methods of operation are also discussed.

Abstract: A container storing a liquid anesthetic solution is disclosed. The container is sealed by a closure, and the liquid anesthetic solution includes an anesthetic being from 0.1% to 10% by weight of the liquid anesthetic solution, water, and a solvent. The container includes a material that is inert to the anesthetic, and the closure includes siliconized rubber, a fluoropolymer, or metal that is inert to the anesthetic. The concentration of the anesthetic in the liquid anesthetic solution stored in the container following a predetermined time period is at least 93% of a concentration of the anesthetic in the liquid anesthetic solution before the liquid anesthetic solution is stored in the container.

Abstract: An apparatus and method for a converting tensor data. For example, one embodiment of a method comprises: fetching source tensor blocks of a source tensor data structure, each source tensor block comprising a plurality of source tensor data elements having a first numeric representation, wherein the source tensor data structure comprises a predefined structural arrangement of source tensor blocks; converting the one or more source tensor blocks into one or more destination tensor blocks comprising a plurality of destination tensor data elements having a second numeric representation different from the first numeric representation, wherein the sets of one or more source tensor blocks are converted to one or more corresponding destination tensor blocks in a specified order based on the first and second numeric representations; and storing each individual destination tensor block in a designated memory region to maintain coherency with the predefined structural arrangement of the source tensor blocks.

Abstract: A multistage amplifier for outputting a first output signal includes: an input stage circuit, a middle stage circuit and an output stage circuit. The input stage circuit includes at least one amplifying circuit, which receives the first output signal and a reference signal, thereby to generate a second output signal at an output terminal of the input stage circuit. The middle stage circuit is used to perform frequency compensation on the multistage amplifier. The output stage circuit is used to generate the first output signal at an output terminal of the output stage circuit according to the second output signal. The output stage circuit includes at least one current limiting circuit, where the current limiting circuit is controlled by the second output signal, thereby to adjusting a voltage level of the first output signal.

Abstract: A pilot signal detection and indication unit includes a pilot signal scaling unit structured to generate a scaled pilot signal by shifting a pilot signal using a bias voltage and scaling down the pilot signal, a pilot signal duty cycle comparator unit structured to generate a limited pilot signal that has a fixed peak voltage and a duty cycle that is equivalent to the duty cycle of the pilot signal, a processing unit structured to determine a voltage value and the duty cycle value of the pilot signal from the scaled pilot signal and the limited pilot signal, and to generate an indication signal based on the determined voltage value and duty cycle value, and an indication unit having a number of indicators and being structured to activate selected ones of the number of indicators based on the indication signal.

Abstract: An electronic device that is configured to be coupled to an alternating current (AC) power unit that includes an AC input power signal is described. The electronic device includes a reference signal generator circuit that is configured to generate a reference signal based on a direct current (DC) power source, a voltage divider circuit that is configured to scale the reference signal for application to the AC input power signal to generate a divided AC input power signal, an amplifier circuit that is configured to output a fault indication signal responsive to the divided AC input power signal, and an amplifier control circuit that is coupled to the amplifier circuit and is configured to control a fault indication signal level of the fault indication signal that is output by the amplifier circuit. Related methods and computer program products are also described.

Abstract: A pilot signal detection and indication unit includes a pilot signal scaling unit structured to generate a scaled pilot signal by shifting a pilot signal using a bias voltage and scaling down the pilot signal, a pilot signal duty cycle comparator unit structured to generate a limited pilot signal that has a fixed peak voltage and a duty cycle that is equivalent to the duty cycle of the pilot signal, a processing unit structured to determine a voltage value and the duty cycle value of the pilot signal from the scaled pilot signal and the limited pilot signal, and to generate an indication signal based on the determined voltage value and duty cycle value, and an indication unit having a number of indicators and being structured to activate selected ones of the number of indicators based on the indication signal.

Abstract: Self-powered switches include a switch housing having an externally accessible user input member, a coil assembly, and a magnet arranged therein such that at least one of the coil assembly and the magnet move relative to each other responsive to movement of the user input member between first and second switch positions, and a control circuit held in the switch housing and coupled to first and second terminals of the coil assembly. The control circuit is configured to detect respective electrical characteristics of the first and second terminals of the coil assembly responsive to the movement of the user input member, and selectively transmit first and second wireless control signals to a remote receiver based on the respective electrical characteristics of the first and second terminals of the coil assembly, respectively. Related circuits and methods of operation are also discussed.

Abstract: Disclosed embodiments relate to sparse matrix multiplication (SMM) acceleration using column folding and squeezing. In one example, a processor, in response to a SMM instruction having fields to specify locations of first, second, and output matrices, the second matrix being a sparse matrix, uses execution circuitry to pack the second matrix by replacing one or more zero-valued elements with non-zero elements yet to be processed, each of the replaced elements further including a field to identify its logical position within the second matrix, and, the execution circuitry further to, for each non-zero element at row M and column K of the specified first matrix, generate a product of the element and each corresponding non-zero element at row K, column N of the packed second matrix, and accumulate each generated product with a previous value of a corresponding element at row M and column N of the specified output matrix.

Abstract: Self-powered switches include a switch housing having an externally accessible user input member, a coil assembly, and a magnet arranged therein such that at least one of the coil assembly and the magnet move relative to each other responsive to movement of the user input member between first and second switch positions, and a control circuit held in the switch housing and coupled to first and second terminals of the coil assembly. The control circuit is configured to detect respective electrical characteristics of the first and second terminals of the coil assembly responsive to the movement of the user input member, and selectively transmit first and second wireless control signals to a remote receiver based on the respective electrical characteristics of the first and second terminals of the coil assembly, respectively. Related circuits and methods of operation are also discussed.

Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.