Abstract: An organic solvent is separated from a waste stream containing supercritical CO2, an organic solvent and etchant contaminants. The process includes separating the supercritical CO2 by subjecting the waste stream to elevated temperature and/or reduced pressure to thereby obtain a first composition containing the supercritical CO2 and a second composition containing the organic solvent and being substantially free of the supercritical CO2; and then removing non-volatile etching contaminants from the second stream search as by at least one of the following: evaporation; distillation; filtration; centrifugation; and settling.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: A method for forming a dielectric structure. A first layer is formed, wherein the first layer includes a first fully cured photoimageable dielectric (PID) material. A sticker lays is nonadhesively formed on the first layer, wherein the sticker layer includes a partially cured PID material. A second layer is nonadhesively formed on the sticker layer, wherein the second layer includes a second fully cured PID material, wherein the sticker layer is nonadhesively sandwiched between the first layer and the second layer such that the sticker layer is in non-adhesive contact with the first layer and in non-adhesive contact with the second layer, and wherein the sticker layer is capable of remaining in non-adhesive contact with the first layer and the second layer until the sticker layer is subsequently subjected to additional curing.

Abstract: The present invention provides a printed circuit board and a method for the production of a printed circuit board having fine-line circuitry and greater aspect ratio on a subcomposite with plated through holes. A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: An organic solvent is separated from a waste stream comprising supercritical CO2, an organic solvent and etchant contaminants.

Abstract: A dielectric structure, and an associated method of fabrication, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The partially cured PID layer be formed either in isolation, or by successively forming upon one of the fully cured PID layers: the first partially cured PID sheet, the power plane, and the second partially cured PID sheet. The first partially cured PID sheet and the second partially cured PID sheet is the result of partially curing, by radiative exposure, a first uncured PID sheet and a second uncured PID sheet, respectively. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer.

Abstract: A dielectric structure, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured and nonadhesively coupled to one of the fully cured PID layers. The dialectric structure may further include a second PID film partially cured and nonadhesively coupled to the other fully cured PID layer.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A method for conductively filling a hole or via disposed in an electronic package to provide a structure having a lower coefficient of thermal expansion. After fabricating a through hole or a plated through hole in an electronic package, the hole or via is filled with metal, and the surface of the electronic package is sealed.

Abstract: An organic solvent is separated from a waste stream comprising hydrofluoric acid, an organic solvent and etchant contaminants. The process comprises separating the hydrofluoric acid by subjecting the waste stream to at least one of the following processes: ion exchange; extraction of the hydrofluoric acid; electrophoresis; converting the hydrofluoric acid to an insoluble salt; to thereby obtain a first composition containing the hydrofluoric acid and a second stream containing the organic solvent and being substantially free of the hydrofluoric acid; and then distilling the second stream to recover the organic solvent free of the etching contaminants.

Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

Abstract: A method provides for additive platinum on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surfaces of the printed circuit board. These plated through holes contain a bill composition.