Patents by Inventor Anindya Bhattacharya

Anindya Bhattacharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11799426
    Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Cirrus Logic Inc.
    Inventors: Johnny Klarenbeek, David P. Singleton, Morgan T. Prior, Jonathan T. Wigner, Christopher M. Dougherty, Qi Cai, Anindya Bhattacharya
  • Patent number: 11782101
    Abstract: A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 10, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Prashanth Drakshapalli, John L. Melanson, Anindya Bhattacharya, Seung Bae Lee
  • Publication number: 20230285459
    Abstract: Compositions and methods of using ILC2 to reduce microglial activation or to reduce blood-brain barrier (BBB) permeability are described. Also described are methods and compositions that use an agent that increases the number of activated ILC2 to reduce microglial activation or BBB permeability.
    Type: Application
    Filed: April 27, 2023
    Publication date: September 14, 2023
    Inventors: German Rodrigo Aleman Muench, Homayon Banie, Anindya Bhattacharya, Noel Christopher Derecki, Pejman Soroosh
  • Publication number: 20230262404
    Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.
    Type: Application
    Filed: March 21, 2023
    Publication date: August 17, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Anindya BHATTACHARYA, Bhoodev KUMAR, Jaimin MEHTA, Yongsheng SHI, Aleksey S. KHENKIN, John L. MELANSON
  • Publication number: 20230170850
    Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Johnny KLARENBEEK, David P. SINGLETON, Morgan T. PRIOR, Jonathan T. WIGNER, Christopher M. DOUGHERTY, Qi CAI, Anindya BHATTACHARYA
  • Patent number: 11641558
    Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: May 2, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Anindya Bhattacharya, Bhoodev Kumar, Jaimin Mehta, Yongsheng Shi, Aleksey S. Khenkin, John L. Melanson
  • Publication number: 20230113378
    Abstract: The disclosure relates to methods of treating multiple sclerosis and maintaining or maximizing vaccine effectiveness. In certain aspects, the methods comprise administrating ponesimod, administering a vaccine, and interrupting the administration of the ponesimod.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 13, 2023
    Inventors: Krista Spiller, Anindya Bhattacharya, Tatiana Sidorenko, Janice Wong
  • Patent number: 11489534
    Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Seung Bae Lee, Sunny Bhagia, Jaiminkumar Mehta, Anindya Bhattacharya, John L. Melanson
  • Publication number: 20220215901
    Abstract: The present disclosure describes a sequencing system configured to identify structural variants in mitochondrial DNA. Variant callers configured to identify variants in linear genomes (e.g., those found in chromosomes) can fail to properly identify structural variants in mitochondrial DNA. The system and methods can identify structural variants in next generation sequencing data collected from circular, mitochondrial DNA.
    Type: Application
    Filed: May 26, 2020
    Publication date: July 7, 2022
    Applicant: Quest Diagnostics Investments LLC
    Inventor: Anindya Bhattacharya
  • Patent number: 11316523
    Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: April 26, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Saurabh Singh, Jaimin Mehta, Sriram Balasubramanian, Anindya Bhattacharya
  • Patent number: 11290120
    Abstract: A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: March 29, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Seung Bae Lee, John L. Melanson, Anindya Bhattacharya, Prashanth Drakshapalli
  • Publication number: 20220070600
    Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 3, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Anindya BHATTACHARYA, Bhoodev KUMAR, Jaimin MEHTA, Yongsheng SHI, Aleksey S. KHENKIN, John L. MELANSON
  • Publication number: 20220045689
    Abstract: A data acquisition system (DAS) for processing an input signal from a resistive sensor (e.g., Hall effect sensor) includes a sensor signal path that digitizes the input signal. An input impedance of the sensor signal path attenuates the input signal. A gain error corrector applies a gain error correction factor in a digital domain of the DAS to the digitized input signal to compensate for a loading effect to the resistive sensor. The sensor signal path includes an inverting amplifier that provides low distortion for the input signal and an ADC (e.g., delta-sigma, SAR, pipelined, auxiliary) that digitizes the input signal. A sensor characterization path digitizes the sensor resistance which the gain error corrector uses, along with the inverting amplifier input impedance, to calculate the gain error correction factor.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Seung Bae Lee, John L. Melanson, Anindya Bhattacharya, Prashanth Drakshapalli
  • Publication number: 20220043077
    Abstract: A data acquisition system (DAS) for acquiring data from a Hall effect sensor includes one or more state variables, a multiplexer that periodically rotates a signal from the Hall effect sensor, and a controller that resets the one or more state variables in synchronization with rotation of the signal. The state variables may be digital states in a digital memory or voltages of capacitors the controller forces to a reset voltage. The state variables may be included in a noise-shaping SAR ADC, a delta-sigma ADC, a digital filter, an integrator, an analog filter, a VCO, an incremental ADC or an auxiliary ADC-assisted incremental ADC, or an auxiliary ADC of the DAS.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Inventors: Prashanth Drakshapalli, John L. Melanson, Anindya Bhattacharya, Seung Bae Lee
  • Publication number: 20210313011
    Abstract: The systems and methods discussed herein can calculate sequencing statistics such as coverage depth for sequencing data. The present solution can determine variant frequencies and identify clinically relevant variants. The present solution can read BAM and VCF input files and Phred scaled quality scores. The present solution can select relatively high quality reads based on the quality scores and can calculate reference and alternative allele counts for SNPs, insertions and deletions (INDELs), and structural variants.
    Type: Application
    Filed: October 16, 2019
    Publication date: October 7, 2021
    Applicant: Quest Diagnostics Investments LLC
    Inventors: Anindya Bhattacharya, Anna Gerasimova, Quoclinh Nguyen, Christopher Elzinga, Edward Moler
  • Publication number: 20210286393
    Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.
    Type: Application
    Filed: March 11, 2020
    Publication date: September 16, 2021
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Christopher M. DOUGHERTY, Anindya BHATTACHARYA, Vaibhav PANDEY, Ying OU
  • Patent number: 11119524
    Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: September 14, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Christopher M. Dougherty, Anindya Bhattacharya, Vaibhav Pandey, Ying Ou
  • Patent number: 10571484
    Abstract: In accordance with embodiments of the present disclosure, an apparatus for measuring acceleration may include a spring-mounted mass, a positional encoder configured to measure a position of the spring-mounted mass and output one or more signals indicative of a sine and a cosine of the position, a driver to set and maintain an oscillation of the spring-mounted mass, and a decoder configured to process the one or more signals to calculate an acceleration of the spring-mounted mass.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 25, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: John L. Melanson, Anindya Bhattacharya, Roderick D. Holley, Ruoxin Jiang, Stephen T. Hodapp, John C. Tucker
  • Publication number: 20200016205
    Abstract: Compositions and methods of using ILC2 to reduce microglial activation or to reduce blood-brain barrier (BBB) permeability are described. Also described are methods and compositions that use an agent that increases the number of activated ILC2 to reduce microglial activation or BBB permeability.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 16, 2020
    Inventors: German Rodrigo Aleman Muench, Anindya Bhattacharya, Noel Christopher Derecki, Pejman Soroosh
  • Publication number: 20190037327
    Abstract: An apparatus for biasing a plurality of microphones includes a sensing circuit that actively senses a local ground reference for each microphone. An intermediate stage receives a constant non-local reference voltage as an input and responsively provides a respective constant local reference signal (e.g., current) with respect to each of the actively sensed local ground references. For each microphone, a respective microphone bias block uses the respective constant local reference signal to generate a respective constant local microphone bias voltage to bias the microphone. For each microphone, a variable RC network uses the respective constant local reference current to generate a constant local reference voltage for the microphone. Each RC network is controllable in response to the respective actively sensed local ground reference to independently set the respective local microphone bias voltage.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 31, 2019
    Inventors: Anindya Bhattacharya, Bhoodev Kumar, John L. Melanson, Vivek Oppula, Anuradha Parsi, Qi Cai