Abstract: Sensing electronics may be used to measure capacitance of components, such as speakers in mobile devices. A sensing circuit may include a charge-sense front end with sine wave excitation, an analog-to-digital conversion block, and a digital demodulator. The component being measured by the sensing electronics may be excited by a high-frequency sine wave excitation. The digitization of the output from the component may be performed using a bandpass filter synchronized with the excitation signal by centering the bandpass filter near (e.g., within 5% of) the frequency of the excitation signal.

Abstract: A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.

Abstract: In accordance with embodiments of the present disclosure, a comparator may include a transconductance stage having an input configured to receive an input voltage and generate an intermediate current responsive to the input voltage, a hysteretic current source configured to generate a hysteretic current, an output stage configured to generate an output signal based at least on the intermediate current, and a switch responsive to the output stage and configured to combine the intermediate current and the hysteretic current to generate a combined current, such that the output stage generates the output signal based at least on the intermediate current and the hysteretic current when output signal has a first value.

Abstract: A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.

Abstract: A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.

Abstract: In accordance with embodiments of the present disclosure, an apparatus for measuring acceleration may include a spring-mounted mass, a positional encoder configured to measure a position of the spring-mounted mass and output one or more signals indicative of a sine and a cosine of the position, a driver to set and maintain an oscillation of the spring-mounted mass, and a decoder configured to process the one or more signals to calculate an acceleration of the spring-mounted mass.

Abstract: A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than or equal to 2 and wherein the n-stage stacked charging circuit may comprise n?1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n?1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n?1th discharging time period through the respective n?1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Abstract: A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

Abstract: A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than one which may comprise n?1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n?1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n?1th discharging time period through the respective n?1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Abstract: The system contains a first input receiving a signal from the amplifier input. A second input receives a signal from the amplifier output. A gain modification device is connected to the second input thereby reducing an amplitude of the signal from the amplifier output. A difference element connected to the gain modification device and the first input subtracts one of the first input and the second input from the other of the first input and the second input and outputting a difference voltage. A comparator, connected to the difference element and a threshold voltage source, compares the difference voltage to a threshold voltage. A disabling device is connected to the comparator and an output stage of the amplifier, wherein an output stage of the amplifier is disabled when the threshold voltage exceeds the difference voltage.

Abstract: A peak junction temperature monitoring system for a semiconductor device includes a peak power dissipation sensor for sensing the peak power dissipation in the device. A temperature sensor senses an average temperature of the device, and a peak junction temperature computation circuit generates a signal representative of a peak junction temperature based on input from the peak power dissipation sensor and the temperature sensor.

Abstract: A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

Abstract: The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.

Abstract: The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.

Abstract: A differential amplifier stage includes one active load circuit connected to a pair of cross-coupled transistors that produce a differential signal. The active load circuit controls the rise time of the differential signal. The differential amplifier stage also includes another active load circuit connected to the pair of cross-coupled transistors. The second active load circuit controls the fall time of the differential signal.

Abstract: An embodiment includes a plurality of tangible electronic elements interconnected to form a forgetful latch. The forgetful latch includes a pass element operable to receive input pulses; a biasing element coupled to the pass element and operable to bias a storage node charged by at least one of the input pulses; and an inverter coupled to the biasing elements and operable to produce an output pulse that stretches the input pulses.