Abstract: An integrated circuit including an FPGA having an input to receive an input data stream which includes a first portion and a second portion, processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation, and an output to output the processed data. The integrated circuit further includes logic circuitry, separate from the FPGA, including an input to receive the input data stream, data alignment circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry, and data combining circuitry to generate an output data stream using the processed data from the FPGA and the second portion of the input data stream received from the data alignment circuitry.

Abstract: An integrated circuit comprising a field programmable gate array (FPGA) including a plurality of logic tiles wherein each logic tile includes circuitry including (i) logic circuitry and (ii) an interconnect network including a plurality of multiplexers. The FPGA further includes a robust memory cell including: three or more storage elements that are more than one time programmable to store a data state, majority detection circuitry to detect a majority data state stored in the three or more storage elements; and an output, coupled to the majority detection circuitry, to output mode select data which is representative of the majority data state stored in the storage elements. The FPGA also includes mode/function select circuitry to configure a mode of operation of at least a portion of the circuitry in one or more of the plurality of logic tiles based on the mode select data.

Abstract: An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.

Abstract: An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.

Abstract: An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.

Abstract: An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.

Abstract: An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.

Abstract: A computing device is described. The computing device a processor, a bus coupled to the processor, a graphics display device, coupled to the bus, to display graphics data, an interactive display device, coupled to the bus, to display bitmap image data and a manager module to manage the bitmap image data and transmit the bitmap image data to the interactive display device.

Abstract: Disclosed is an apparatus and method for automatically configuring a mobile device. A mobile device can include a touch sensitive display, a processor, and a plurality of sensors to collect sensor data associated with the mobile device. The mobile device may establish an orientation of the mobile device relative to a user of the mobile device based on the sensor data. The mobile device may then determine a usage context for the mobile device based at least on the established orientation of the mobile device relative to the user. Furthermore, the mobile device may configure one or more components of the mobile device based on the determined usage context.

Abstract: A computing device is described. The computing device a processor, a bus coupled to the processor, a graphics display device, coupled to the bus, to display graphics data, an interactive display device, coupled to the bus, to display bitmap image data and a manager module to manage the bitmap image data and transmit the bitmap image data to the interactive display device.

Abstract: Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by an voltage offset value programmed by an offset code received at the control input of the voltage offset block and a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage output register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage level of a selected voltage offset block, at the control output port coupled to the selected voltage offset block.

Abstract: Disclosed is an apparatus and method for automatically configuring a mobile device. A mobile device can include a touch sensitive display, a processor, and a plurality of sensors to collect sensor data associated with the mobile device. The mobile device may establish an orientation of the mobile device relative to a user of the mobile device based on the sensor data. The mobile device may then determine a usage context for the mobile device based at least on the established orientation of the mobile device relative to the user. Furthermore, the mobile device may configure one or more components of the mobile device based on the determined usage context.

Abstract: A system and method for video content sharing are given. A wireless controller of a first computing device receives a multi-gigabit-per-second transmission of a compressed and encrypted remote frame buffer from a second computing device, and stores the compressed and encrypted remote frame buffer in local memory. An integrated graphics controller of the first computing device decompresses and decrypts the remote frame buffer, and renders a composite frame buffer of the remote frame buffer and a native or local frame buffer of the first computing device.

Abstract: A system and method for video content sharing are given. A wireless controller of a first computing device receives a multi-gigabit-per-second transmission of a compressed and encrypted remote frame buffer from a second computing device, and stores the compressed and encrypted remote frame buffer in local memory. An integrated graphics controller of the first computing device decompresses and de-crypts the remote frame buffer, and renders a composite frame buffer of the remote frame buffer and a native or local frame buffer of the first computing device.

Abstract: Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by an voltage offset value programmed by an offset code received at the control input of the voltage offset block and a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage output register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage level of a selected voltage offset block, at the control output port coupled to the selected voltage offset block.

Abstract: Disclosed are novel methods and apparatus for provision of efficient, effective, and/or flexible computer system layout and/or cooling configuration. In accordance with an embodiment of the present invention, a method of cooling a computer system is disclosed. The computer system may include a plurality of heat generating electrical components that require cooling. The method includes: providing at least two cooling fans arranged front to back of the computer system to create a push (inlet) and pull (outlet) airflow to cool the computer system and providing a plurality of temperature sensors located at various locations within the computer system to sense a local temperature.

Abstract: An apparatus for testing an integrated circuit chip includes a printed circuit device having connector pads, contacts, and traces extending between at least some of the connector pads and the contacts. The printed circuit device has openings therethrough, intersecting the contacts, that are adapted to receive the pins extending from the integrated circuit chip so that the contacts may electrically contact the pins extending from the integrated circuit chip. The apparatus further includes a connector electrically interconnected with at least some of the connector pads. The apparatus is adapted to be disposed between the integrated circuit chip and a chip socket, such that the pins extending from the integrated circuit chip may be inserted through the printed circuit device and into the chip socket.

Abstract: Disclosed are novel methods and apparatus for provision of efficient, effective, and/or flexible computer system layout and/or cooling configuration. In accordance with an embodiment of the present invention, a method of cooling a computer system is disclosed. The computer system may include a plurality of heat generating electrical components that require cooling. The method includes: providing at least two cooling fans arranged front to back of the computer system to create a push (inlet) and pull (outlet) airflow to cool the computer system and providing a plurality of temperature sensors located at various locations within the computer system to sense a local temperature.

Abstract: An enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion the base. A computer system includes a motherboard having a central processing unit, a power supply capable of supplying power to the motherboard, and an enclosure capable of housing the motherboard and the power supply. The enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion of the base.

Abstract: An apparatus for testing an integrated circuit chip includes a printed circuit device having connector pads, contacts, and traces extending between at least some of the connector pads and the contacts. The printed circuit device has openings therethrough, intersecting the contacts, that are adapted to receive the pins extending from the integrated circuit chip so that the contacts may electrically contact the pins extending from the integrated circuit chip. The apparatus further includes a connector electrically interconnected with at least some of the connector pads. The apparatus is adapted to be disposed between the integrated circuit chip and a chip socket, such that the pins extending from the integrated circuit chip may be inserted through the printed circuit device and into the chip socket.