Abstract: An enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion the base. A computer system includes a motherboard having a central processing unit, a power supply capable of supplying power to the motherboard, and an enclosure capable of housing the motherboard and the power supply. The enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion of the base.

Abstract: A computer assembly includes a motherboard having a first bus extending to a first connector and a riser card having a second bus extending to a plurality of connectors and extending to a second connector adapted to mate with the first contact set of the motherboard to couple the first bus with the second bus. The computer assembly further includes a first expansion card having a third bus extending to a third connector adapted to mate with one of the plurality of connectors of the riser card to couple the third bus with the second bus. A method includes driving a first signal onto a motherboard bus, transmitting the first signal over the motherboard bus to a riser card bus, and transmitting the first signal over the riser card bus to a plurality of expansion card buses.

Abstract: A high performance peripheral interface device is coupled to a computer via a computer bus and is coupled to a peripheral via a peripheral bus. To speed accessing of consecutively addressed data (the nth datum and the n+1th datum) from the peripheral, the interface device reads the n+1th datum from the peripheral: 1) before the computer has requested the n+1th datum from the interface device, and 2) while the computer is accessing the nth datum from the interface device.

Abstract: A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. The LBPI is coupled between the computer local bus and the peripheral interface(s) and has a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. The LPBI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active.