Abstract: Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s?, c?) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: A health-related emergency mobile alert system to facilitate communication, care and intervention during critical events. The system communicates with medical monitors, which measure and collect a subject's physiological data and vital signs information. A service provider maintains a database with the subject's medical records and an emergency contact list. When a critical event is detected, a two-way mobile communication device that is configured to communicate with the medical monitor transmits the physiological data and location coordinates of the subject to the service provider, and a conference call with members of the emergency contact list is initiated to help facilitate aid to the subject. The two-way mobile communication device may include a speaker and GPS technology. It may also include self-activating features wherein pre-recorded messages conveying potential dangers are transmitted to the subject when the subject's physiological data and vital signs reflect precarious levels.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: An apparatus for transmitting signals over a signal line includes a transmitter with an output connectable to the signal line, for a synchronization signal in a power saving mode and a wanted signal in a normal mode of operation, wherein the synchronization signal has a reduced amplitude as compared to an amplitude of the wanted signal and has a periodic data pattern so that the synchronization signal permits maintaining an alignment of the synchronization signal and a reference signal in the receiver.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

Abstract: A collapsible decoy 10, including two generally planar side body panels 11, 12 allowing the decoy 10 to be collapsed into a substantially flat configuration and which are splayed when in the erected position, a head and neck portion 14 connected to at least one of the side body panels 11, 12, and a means for retaining the side body panels 11, 12, when in use, in the erected position.

Abstract: The present invention refers to a memory system with a controller and a memory device with a communication channel with a data path and a timing path coupling the controller with the memory device. The communication channel has different propagation times for the data path and the timing path exchanging a information signal and a timing signal between the controller and the memory device. The timing signals are used for determining the value of the information signal, and a retiming circuit that is connected with the communication channel compensates, depending on a compensation signal on an input, the delay between the data path and the timing path for exchanging a information signal and a timing signal between the controller and the memory device.

Abstract: A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

Abstract: A clock and data recovery circuit including a first circuit and a second circuit. The first circuit is configured to receive a clock signal and a phase control signal and to lock onto the clock signal and provide a cleaned clock signal. The second circuit is configured to receive a data signal and the cleaned clock signal and to sample the data signal via the cleaned clock signal and provide the phase control signal. The first circuit adjusts the phase of the cleaned clock signal based on the phase control signal.

Abstract: A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate sampling points between the data sampling points to obtain intermediate samples. The data is corrected at at least one intermediate sampling point of the intermediate sampling points depending on at least one of a previous data sample sampled at a data sampling point preceding the at least one intermediate sampling point and a previous intermediate sample sampled at a data sampling point preceding the at least one intermediate sampling point.

Abstract: Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals. A method and an arrangement are provided for generating an output clock signal (o), in which a plurality of input clock signals (s, c) that have a predetermined phase relationship to one another, are weighted with respective weighting factors (A, 1-A), and in which the weighted input clock signals (s?, c?) are added in order to generate a summated clock signal (i). The summated clock signal (i) is integrated in an integrator (8) and optionally amplified in order to generate the output clock signal (o). An output clock signal (o) with an adjustable phase relation can be generated with such a method and such an arrangement, in which the requirements placed on the input clock signals are less stringent.

Abstract: The invention provides a clock signal extraction device for extracting a clock signal from a periodic data signal, comprising a phase detector (104, 106) for detecting a first phase difference between rising edges of said data signal and a rising edges clock signal and for detecting a second phase difference between falling edges of said data signal and a falling edges clock signal; and a clock generator (110, 112) for generating said rising edges clock signal so that said first phase difference is minimized, for generating said falling edges clock signal so that said second phase difference is minimized, and for generating said clock signal in dependence on said first phase difference and said second phase difference. The invention further provides a method for extracting a clock signal from a periodic data signal.

Abstract: The invention relates to an LVDS driver for small supply voltages, particularly of less than 2.0 V, for producing a differential output signal (Pout, Nout), having a pull-up transistor (P3, P4) and a pull-down transistor (P1, P2), respectively, for switching the output voltages which are output at the outputs (Pout, Nout). An optimum switching response and hence an undistorted differential signal can be produced by virtue of the pull-up and pull-down transistors (P1–P4) being in the form of PMOS transistors.

Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: The invention relates to an LVDS driver for small supply voltages, particularly of less than 2.0 V, for producing a differential output signal (Pout, Nout), having a pull-up transistor (P3, P4) and a pull-down transistor (P1, P2), respectively, for switching the output voltages which are output at the outputs (Pout, Nout). An optimum switching response and hence an undistorted differential signal can be produced by virtue of the pull-up and pull-down transistors (P1-P4) being in the form of PMOS transistors.

Abstract: A collapsible decoy 10, including two generally planar side body panels 11, 12 allowing the decoy 10 to be collapsed into a substantially flat configuration and which are splayed when in the erected position, a head and neck portion 14 connected to at least one of the side body panels 11, 12, and a means for retaining the side body panels 11, 12, when in use, in the erected position.

Abstract: The invention relates to a compensation circuit for driver circuits having a current reference source which generates at least one reference signal which is modulated with respect to an input signal, having a current-comparison source which generates at least one comparison signal which is modulated with respect to the input signal, the modulated comparison signals having an inverse characteristic to that of the modulated reference signals in respect of the parameters to be modulated, having a comparison unit to which the modulated reference signals and the modulated comparison signals are fed and which generates from a comparison of these modulated modulating signals at least one digital output signal which can be fed to driver circuits connected downstream.