Abstract: A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.

Abstract: A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.

Abstract: A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied.

Abstract: The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

Abstract: A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.

Abstract: A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

Abstract: An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.

Abstract: An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.

Abstract: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

Abstract: An integrated circuit (IC) device is provided that includes at least one internal voltage regulator arranged to receive a voltage supply signal at a first input thereof, receive a control signal at a second input thereof, regulate the received voltage supply signal in accordance with the received control signal, and provide a regulated voltage supply signal at an output thereof. The IC device further includes at least one voltage regulation power control module operably coupled to the second input of the at least one internal voltage regulator and arranged to provide the control signal thereto. The voltage regulation power control module is further arranged to receive at least one IC device conditional indication, and generate the control signal for the at least one internal voltage regulator based at least partly on an available thermal power budget for the IC device corresponding to the at least one IC device conditional indication.

Abstract: There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.

Abstract: An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops.

Abstract: A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied.

Abstract: A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.

Abstract: The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.

Abstract: An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units. The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units.

Abstract: There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power grid switch locations relative to each of the plurality of operational cells, deriving a cost function based upon the determined timing data, determined switching activity from RTL/design constraints and determined relative power grid switch locations and initially placing the plurality of operational cells according to the derived cost function.

Abstract: A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.

Abstract: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby c

Abstract: A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.