Abstract: An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module.

Abstract: There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.

Abstract: A device for evaluating connectivity between a video driver and a display, the device comprises a first video driver, a first output connector, a first terminating resistance; wherein the device is characterized by comprising a first comparison unit; wherein the first video driver has an output port that is coupled to the first output connector, to the first terminating resistance and to the first comparison unit; wherein the first output connector is configured to be coupled via a first cable to a first input of the display; wherein the first comparison unit is adapted to perform comparisons between a voltage level on the first terminating resistance to multiple thresholds and to determine whether a display first input impedance is substantially equal to the first terminating resistance, whether the display first input impedance is substantially lower then the first terminating resistance, or whether the first video driver is disconnected from the display; wherein the comparisons are executed during a pixel

Abstract: An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops.

Abstract: An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units.

Abstract: There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to load data directly from the external connection into the processor cache memory and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit operably coupled to a processor cache memory and an external connection operably coupled to the central processing unit and processor cache memory, comprising loading data directly from the external connection into the processor cache memory and modifying a source address for said data to become indicative of a location other than from the external connection.

Abstract: A multi-core processor includes a plurality of power gating elements for controlling power applied to each core. Each power gating element is coupled to a respective power gating controllers for controlling the respective power gating element to selectively provide full power to the respective core only during an active period of the respective core. A common power gating controller is coupled to the individual power gating controllers for controlling the individual power gating controllers to balance the active periods of the plurality of cores so as to substantially reduce or minimise overlapping active periods so as to reduce the total power provided to all the cores.

Abstract: A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimisation comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimisation, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.

Abstract: A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.

Abstract: A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit vi

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transisto

Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.

Abstract: A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits.

Abstract: An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

Abstract: An integrated circuit comprising at least one signal path for a timing sensitive signal. At least one section of the signal path comprises a first section path comprising a first propagation timing factor, at least one further section path comprising a second propagation timing factor different to the first propagation timing factor, and a path selection component arranged to enable the selection of one of the first and at least one further section paths via which the timing sensitive signal is to propagate through the at least one section of the signal path based on at least one from a group consisting of: the first propagation timing factor, second propagation timing factor.

Abstract: An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.

Abstract: An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.

Abstract: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

Abstract: A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.