Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Abstract: Secure vehicular part communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and a vehicular communication component coupled to the processing resource. The vehicular communication component can be configured to, in response to receiving a part public key and a part signature from a part communication component associated with a vehicular part, verify an identity of the vehicular part based on the part signature. The vehicular communication component can be configured to, in response to verifying the identity, generate a vehicular public key. The vehicular communication component can be configured to encrypt vehicular data using the part public key. The vehicular communication component can be configured to provide the vehicular public key and the vehicular data to the part communication component.

Abstract: System and techniques for a secure wireless lock-actuation exchange are described herein. After receiving a request to actuate a lock from a device, a controller can calculate a challenge counter and then perform verification iterations until an end condition is met—which is a failure of a verification iterations or the number of iterations reaches the challenge count. If the verification iterations reach the challenge count (e.g., there are no failed iterations), then the controller actuates the lock. Each iteration includes an exchange between the device and the controller that the device validates by signing a message with a private key shared by the device and the controller. The exchange also includes a freshness value integrated into the device validation to prevent replay attacks.

Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

Abstract: The present disclosure includes methods and apparatuses comprising a processor and an external communication component coupled to the processor. The external communication component, in response to determining that an approaching entity is within a particular proximity of the external communication component, is configured to generate an external private key and an external public key, provide the external public key to a communication component of the approaching entity, receive data from the communication component of the approaching entity in response to providing the external public key to the communication component of the approaching entity, decrypt the received data using the external private key, and provide authorization to the approaching entity to transit through a limited access gate based on the decrypted received data.

Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Abstract: The present disclosure relates to a memory component for a System-on-Chip (SoC) structure including at least a memory array and at least a logic portion for interacting with the memory array and with the SoC structure wherein the memory component is a structurally independent semiconductor device coupled to and partially overlapping the SoC structure.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: A method and apparatus according to the invention can include energizing a wireless communication device coupled to a processor of a vehicular entity thus establishing a secure channel or communication area around the vehicular entity; exchanging information and data with other vehicular entities entering the established channel or communication area; regulating some vehicle parameters of said vehicular entity for driving the departure and/or travelling of the vehicular entity according to the received information and data.

Abstract: A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.

Abstract: The present disclosure includes apparatuses, methods, and systems for validating data stored in memory using cryptographic hashes. An embodiment includes a memory, and circuitry configured to divide the memory into a plurality of segments, wherein each respective segment is associated with a different cryptographic hash, validate, during a powering of the memory, data stored in each respective one of a first number of the plurality of segments using the cryptographic hash associated with that respective segment, and validate, after the powering of the memory, data stored in a second number of the plurality of segments, data stored in each respective one of a second number of the plurality of segments using the cryptographic hash associated with that respective segment.

Abstract: The present disclosure relates to a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, and a method for checking the erasing phase of the non-volatile device; the method comprises: performing a dynamic erase operation of at least a memory block; storing in a dummy row at least internal block variables of said dynamic erase operation and/or a known pattern.

Abstract: Disclosed are techniques for improving an advanced driver-assistance system (ADAS) using a secure channel area. In one embodiment, a method is disclosed comprising establishing a secure channel area extending from at least one side of a first vehicle; detecting a presence of a second vehicle in the secure channel area; establishing a secure connection with the second vehicle upon detecting the presence; exchanging messages between the first vehicle and the second vehicle, the messages including a position and speed of a sending vehicle; taking control of a position and speed of the first vehicle based on the contents of the messages; and releasing control of the position and speed of the first vehicle upon detecting that the secure connection was released.

Abstract: The present disclosure includes apparatuses, methods, and systems for block chain validation of memory commands. An embodiment includes a memory, and circuitry configured to receive a command that is included in a block in a block chain for validating commands to be executed on the memory, wherein the command includes an anti-replay portion that is based on a previous command included in a previous block in the block chain, validate the command using the anti-replay portion of the command, and execute the command on the memory upon validating the command.

Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication in a traffic control network. An embodiment includes a memory, and circuitry configured to receive a traffic control public key from a traffic control device, wherein the traffic control public key is received in response to providing, to the traffic control device, a request to modify content of the traffic control device, encrypt data corresponding to vehicle information using the traffic control public key, provide, to the traffic control device, the encrypted data to store the data in the traffic control device, and access a network of traffic control devices, including the traffic control device, via the data stored in the traffic control device.

Abstract: The present disclosure includes apparatuses, methods, and systems for secure communication for a key replacement. An embodiment includes a processing resource, memory having a first operator's key, and a vehicular communication component. The vehicular communication component can be configured to provide, to a server, a public key generated along with a private key and decrypt, in response to receipt of a second operator's key (e.g., received in response to providing the public key to the server) encrypted using the public key, the second operator's key using the private key. The vehicular communication component can be configured to replace, in response to decrypting the encrypted second operator's key, the first operator's key with the second operator's key.

Abstract: Computing nodes in a peer-to-peer network that can receive data about an accident in response to a vehicle having an accident. A computing device in the peer-to-peer network can generate a record of the data and store, in persistent storage, a copy of the record. The computing device can also transmit the record, via peer-to-peer connections, to other computing nodes in the network. The nodes in the network, when receiving the record, can each store a copy of the record and broadcast the record to one or more additional computing nodes in the network to cause the one or more additional computing nodes to store one or more additional copies of the record. Also, in response to an inquiry about the accident, the node can provide the record. And the node can participate in a determination of a network consensus in the network about validity of the record.

Abstract: An example apparatus comprises a processing resource coupled to a memory resource. The processing resource may be configured to execute instructions stored on the memory resource to generate a first secure key including a private key stored by a vehicle, generate a first secure message including the first secure key, transmit the first secure message over a vehicle bus to a vehicle part associated with the vehicle, and receive, from the vehicle part, a second secure message including at least one of a vehicle identification number (VIN) and a configuration parameter corresponding to the vehicle part in response to a determination that the first secure key matches a secure key corresponding to the vehicle part.