Abstract: The present disclosure relates to an apparatus comprising a host device and a memory component coupled to the host device. The memory component can comprise an array of memory cells, and an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal.

Abstract: A system on chip includes a monitoring circuit that detects an anomalous behavior of the system on chip. The monitoring circuit compares a behavior of the system on chip to at least one reference parameter representing the anomalous behavior of the system. Using this comparison, the anomalous behavior of the system on chip is detected. An interrupt is the issued in response to the detected anomalous behavior of the system on chip.

Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

Abstract: The present disclosure includes apparatuses, methods, and systems for using a local ledger block chain for secure electronic control unit updates. An embodiment includes a memory, and circuitry configured to receive a global block to be added to a local ledger block chain for validating an electronic control unit update for electronic control unit data stored in the memory, where the global block to be added to the local ledger block chain includes a cryptographic hash of a current local block in the local ledger block chain, a cryptographic hash of the electronic control unit data stored in the memory to be updated, where the current local block in the local ledger block chain has a digital signature associated therewith that indicates the global block is from an authorized entity.

Abstract: The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.

Abstract: Secure medical apparatus communication is described herein. An example apparatus can include a processor and an apparatus communication component. The apparatus communication component can be coupled to the processor and can be configured to, in response to receiving data from an external communication component, generate an apparatus private key and an apparatus public key, provide the apparatus public key and data to the external communication component, receive data from the external communication component in response to providing the apparatus public key and data to the external communication component, decrypt the received data using the apparatus private key, verify an identity of the external communication component, and in response to verifying the identity of the external communication component, perform an operation on the medical apparatus using the received data.

Abstract: A method and apparatus to recognize transported passengers and goods are disclosed herein. One example includes an apparatus comprising a processor unit on a vehicular entity, a communication component coupled to the processor unit, and a memory portion associated to the processor unit and structured to store information and data received through the communication component about at least one of passengers, luggage and/or goods on the vehicular entity, with the communication component being activated by a presence of the at least one of the passengers, luggage and/or goods on the vehicular entity.

Abstract: The present disclosure relates to analyzing a firmware or a finite state machine, decomposing the same into a plurality of routines or states, individuating significative instructions or states, associating each significative instruction or state with a watchpoint, calculating first HASH values of the watchpoints using a HASH function before running the firmware or finite state machine for all allowable paths in the firmware or finite state machine corresponding to a correct working of the same, storing the set of first HASH values as calculated, calculating second HASH values of the watchpoints using a HASH function when running of the firmware or finite state machine, comparing the second HASH value of each watchpoint as calculated with the stored set of first HASH values, and validating the instruction or state of a watchpoint as correct if its second HASH value is comprised in the first HASH values of the allowed paths.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: A memory component comprises a memory unit including an array of memory cells, a controller of the memory unit, and a JTAG test interface including a plurality of contact pads adapted to connect the memory component with a host device and/or a test machine, wherein the test interface further comprises a plurality of test registers, which are configured to store the operating instructions for performing the test of the memory component, and wherein those test registers are organized in a matrix configuration, each row of the matrix being associated with a specific address. A related System-On-Chip device and a related method are further disclosed.

Abstract: Secure emergency vehicular communication is described herein. An example apparatus can include a processing resource, a memory having instructions executable by the processing resource, and an emergency communication component coupled to the processing resource. The emergency communication component can be configured to generate an emergency private key and an emergency public key in response to being within a particular proximity from a vehicular communication component associated with a vehicular entity and in response to receiving a vehicular public key from the vehicular communication component. The emergency communication component can be configured to provide the emergency public key, an emergency signature, and notification data to the vehicular communication component.

Abstract: The present disclosure relates to a memory architecture comprising a plurality of subarrays of memory cells, a plurality of sense amplifiers connected to the subarrays, a plurality of original pads, at least one redundant pad, multiple data lines, and a redundant register connected to the plurality of original pads, to the plurality of redundant pads and to the data lines. The redundant register implementing an interconnection redundancy and connecting one of the redundant pads to the data lines when an addressed original pad is found defective. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory architecture, and an interconnection redundancy managing block included into the memory architecture. A related memory component and related methods for managing interconnection redundancy of the memory architecture and/or the SoC are also disclosed.

Abstract: Disclosed are techniques for remotely controlling autonomous vehicles. In one embodiment, a method is disclosed comprising receiving a message from a first autonomous vehicle, the message including a signed body portion and a triple including components selected from the group consisting of a public identifier of the first autonomous vehicle, a public key of the first autonomous vehicle, and a certificate of the first autonomous vehicle; authenticating the message by verifying the certificate of the first autonomous vehicle; logging the message into a blockchain storage structure, the blockchain storage structure storing a plurality of blocks, each blocking including the signed body portion; and executing one or more orders included within the signed body portion.

Abstract: An example method comprises receiving a number of inputs to a system employing an artificial neural network (ANN), wherein the ANN comprises a number of ANN partitions each having respective weight matrix data and bias data corresponding thereto stored in a memory. The method includes: determining an ANN partition to which the number of inputs correspond, reading, from the memory the weight matrix data and bias data corresponding to the determined ANN partition, and a first cryptographic code corresponding to the determined ANN partition; generating, using the weight matrix data and bias data read from the memory, a second cryptographic code corresponding to the determined ANN partition; determining whether the first cryptographic code and the second cryptographic code match; and responsive to determining a mismatch between the first cryptographic code and the second cryptographic code, issuing an indication of the mismatch to a controller of the system.

Abstract: Disclosed are techniques for providing driver assistance to a non-autonomous vehicle while operating in an autonomous vehicle environment. In one embodiment, a method is disclosed comprising establishing a secure connection with an object selected from a group consisting of a road and lane of a road; receiving, from the object, a packet, the packet describing a condition of the object; validating the packet; generating an augmented display using data within the packet; and displaying the augmented display in a vehicle.

Abstract: A parking system having parking lots and server computers configured to control access to the parking lots. The server computers are connected via a communications network to form a peer to peer network of computing nodes. The peer to peer network of computing nodes hosts a decentralized, distributed database that stores activity records of parking spaces in the parking lots. The peer to peer network can include vehicles planning to use parking services of the parking lots and/or mobile devices connected to infotainment systems of the vehicles. Alternatively, the peer to peer network is formed by parking applications running in the vehicles and/or the mobile devices. The records in the decentralized, distributed database provide parking space availability information and/or can be used to regulate and/or plan parking reservation, usage, and navigational guidance to reach available parking spaces.

Abstract: The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.