Patents by Inventor Antonio Gallerano
Antonio Gallerano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11271392Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.Type: GrantFiled: September 3, 2019Date of Patent: March 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ann Margaret Concannon, Vishwanath Joshi, Antonio Gallerano, Zhao Gao, Yanqing Li
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Patent number: 11239229Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: GrantFiled: November 26, 2018Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Patent number: 11121210Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.Type: GrantFiled: September 4, 2019Date of Patent: September 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Karim-Thomas Taghizadeh Kaschani, Antonio Gallerano
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Publication number: 20200235571Abstract: A protection circuit for a signal processor, a method of operating the protection circuit, and a method of forming the protection circuit. In one example, the protection circuit is couplable to a signal port and a first power bus for the signal processor. The protection circuit includes a first diode string couplable across the signal port and the first power bus. The first diode string includes a first diode and a second diode coupled in series in a same polarity sense. The protection circuit also includes a third diode coupled in parallel with one of the first diode and the second diode in an opposite polarity sense.Type: ApplicationFiled: September 3, 2019Publication date: July 23, 2020Inventors: Ann Margaret Concannon, Vishwanath Joshi, Antonio Gallerano, Zhao Gao, Yanqing Li
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Publication number: 20200006474Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.Type: ApplicationFiled: September 4, 2019Publication date: January 2, 2020Inventors: KARIM-THOMAS TAGHIZADEH KASCHANI, ANTONIO GALLERANO
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Patent number: 10454269Abstract: An electrostatic discharge (ESD) protection circuit includes an active shunt transistor, a first pull-down transistor, and a second pull-down transistor. The active shunt transistor is coupled between a first I/O pad and a reference voltage. The first pull-down transistor is connected to the reference voltage. The second pull-down transistor is connected to the first pull-down transistor and the first I/O pad. The first pull-down transistor and the second pull-down transistor are in separate isolation tanks of an isolation deep n-well.Type: GrantFiled: April 28, 2017Date of Patent: October 22, 2019Assignee: Texas Instruments IncorporatedInventors: Xianzhi Dai, Antonio Gallerano
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Patent number: 10439024Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.Type: GrantFiled: June 13, 2016Date of Patent: October 8, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Karim-Thomas Taghizadeh Kaschani, Antonio Gallerano
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Publication number: 20190109127Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: ApplicationFiled: November 26, 2018Publication date: April 11, 2019Inventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Patent number: 10163888Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: GrantFiled: November 23, 2016Date of Patent: December 25, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Publication number: 20180182749Abstract: An electrostatic discharge (ESD) protection circuit includes an active shunt transistor, a first pull-down transistor, and a second pull-down transistor. The active shunt transistor is coupled between a first I/O pad and a reference voltage. The first pull-down transistor is connected to the reference voltage. The second pull-down transistor is connected to the first pull-down transistor and the first I/O pad. The first pull-down transistor and the second pull-down transistor are in separate isolation tanks of an isolation deep n-well.Type: ApplicationFiled: April 28, 2017Publication date: June 28, 2018Inventors: Xianzhi DAI, Antonio GALLERANO
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Publication number: 20180145064Abstract: Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.Type: ApplicationFiled: November 23, 2016Publication date: May 24, 2018Applicant: Texas Instruments IncorporatedInventors: Antonio Gallerano, Ann Margaret Concannon, Krishna Praveen Mysore Rajagopal
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Publication number: 20170358570Abstract: A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type. First, second and third well regions doped the second dopant type are on top of the BL. Second doped regions doped the first dopant type on top of and contacting the BL arraigned as a first well ring and second well ring are around the first and third well regions respectively. At least one high-injection component including the first well region is surrounded by the first well ring. At least one component including the third well region is surrounded by the second well ring. An npn or pnp guard wall pocket including a wall of the first and second well rings, and the second well region is between the high-injection component and the component.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventors: KARIM-THOMAS TAGHIZADEH KASCHANI, ANTONIO GALLERANO
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Patent number: 8946001Abstract: An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.Type: GrantFiled: January 12, 2012Date of Patent: February 3, 2015Assignee: Altera CorporationInventors: Jeffrey T. Watt, Antonio Gallerano
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Patent number: 8619398Abstract: In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.Type: GrantFiled: February 3, 2012Date of Patent: December 31, 2013Assignee: Altera CorporationInventors: Antonio Gallerano, Charles Y. Chu, Jeffrey T. Watt
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Patent number: 8526147Abstract: In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.Type: GrantFiled: March 28, 2011Date of Patent: September 3, 2013Assignee: National Semiconductor CorporationInventors: Antonio Gallerano, Vladislav Vashchenko
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Patent number: 8497526Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.Type: GrantFiled: October 18, 2010Date of Patent: July 30, 2013Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Antonio Gallerano, Peter J. Hopper
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Publication number: 20120250194Abstract: In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.Type: ApplicationFiled: March 28, 2011Publication date: October 4, 2012Inventors: Antonio Gallerano, Vladislav Vashchenko
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Publication number: 20120091501Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.Type: ApplicationFiled: October 18, 2010Publication date: April 19, 2012Inventors: Vladislav Vashchenko, Antonio Gallerano, Peter J. Hopper
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Patent number: 8120112Abstract: An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.Type: GrantFiled: September 28, 2007Date of Patent: February 21, 2012Assignee: Altera CorporationInventors: Jeffrey T. Watt, Antonio Gallerano
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Patent number: 8116048Abstract: In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.Type: GrantFiled: October 12, 2009Date of Patent: February 14, 2012Assignee: Altera CorporationInventors: Antonio Gallerano, Charles Y. Chu, Jeffrey T. Watt