Abstract: An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.

Abstract: A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors.

Abstract: A conventional ESD protection circuit comprises an SCR and a first diode connected in series between ground and a node or pad to be protected and a second diode connected between ground and the node to be protected. An anode of the first diode and a cathode of the second diode are connected to the node to be protected. In one embodiment of the invention, the capacitance of the second diode is reduced by forming the second diode from a PN junction between a heavily doped region of one conductivity type and a substrate region instead of a well region of the opposite conductivity type. The reduction in the capacitance of the second diode makes it possible to increase the size of the first diode and SCR, thereby decreasing their resistance, while keeping the total capacitance of the ESD circuit at or below the capacitance of the prior art ESD circuit.

Abstract: This relates to a sense circuit to detect an ESD event and turn on an SCR to discharge the ESD event. In a preferred embodiment, the circuit comprises a resistor in the signal path to/from an I/O buffer, a sense circuit in parallel with the resistor, an SCR connected between ground and a node between the resistor and the I/O pad, and an I/O buffer connected between ground and the other end of the resistor. When the sense circuit detects a significant voltage drop across the resistor, it injects current into the SCR, thereby turning on the SCR and discharging the ESD event.

Abstract: A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors.

Abstract: A conventional ESD protection circuit connects a diode and main clamp between a pad or node to be protected and ground. To preserve high speed operation while improving charge device model (CDM) performance, the invention also connects between pad and ground a small diode in series with a secondary clamp and a small isolation resistance. The isolation resistance is approximately 20 ohms. The secondary clamp can be as small as 30 nm wide. Parallel diodes on the main clamp can be replaced with an N+/p-substrate (native) diode 290 to further reduce capacitance.

Abstract: An electrostatic discharge (ESD) protection circuit for protecting a semiconductor device that includes a metal oxide semiconductor field effect transistor (MOSFET) providing a first path from a source of an electrostatic charge to ground. The ESD protection circuit also includes an NPN bipolar transistor providing a second path from the source of the electrostatic charge to ground. The ESD protection circuit also includes a regulation component coupled in series to a base of the NPN bipolar transistor to provide an amount of resistance when the semiconductor device is off and to provide a reduced amount of resistance when the semiconductor device is on.

Abstract: The present invention is an ESD protection circuit that discharges both positive and negative electrostatic events. A preferred embodiment of the circuit comprises a first NMOS transistor having a source and drain connected between ground and an I/O pad and second and third NMOS transistors and a resistor connected in series between ground and the I/O pad. The gate and body of the first transistor and the bodies of the second and third transistors are connected to a node between the second and third transistors; the gate of the second transistor is connected to the I/O pad through a second resistor; and the gate of the third transistor is connected to ground. The second and third transistors maintain the gate and body voltage of the first transistor at the pad voltage when the pad experiences negative voltages and at ground voltage when the pad experiences positive voltages.

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.