Abstract: Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

Abstract: Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

Abstract: Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.

Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.

Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Abstract: A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.