Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: In one or more embodiments, display devices having electrolessly plated conductors and methods are disclosed. One such embodiment is directed to a method of forming a reflective pixel array for a display device, including forming a plurality of conductive pads, each of the conductive pads corresponding to a reflective pixel, and electrolessly plating each of the conductive pads with a reflective conductor.

Abstract: Interconnects containing ruthenium and methods of forming can include utilization of a sacrificial protective material. Planarization or other material removal operations can be performed on a substrate having a recess, the recess containing a ruthenium containing material along with the sacrificial protective material. The protective material is later removed, and a conductor can be filled in the remaining recess.

Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

Abstract: A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents.

Abstract: Isolation of active areas, e.g., transistors, in integrated circuits and the like so that functioning of one active area does not interfere with neighboring ones, is provided by the shallow trench isolation technique followed by chemical-mechanical polishing with a mixed abrasive slurry consisting essentially of (a) relatively large, hard inorganic metal oxide particles having (b) relatively small, soft inorganic metal oxide particles adsorbed on the surface thereof so as to modify the effective charge of the slurry to provide more favorable selectivity of silicon dioxide to silicon nitride, the slurry having a pH below about 5.

Abstract: Isolation of active areas, e.g. transistors, in integrated circuits and the like so that functioning of one active area does not interfere with the neighboring ones, is provided by the shallow trench isolation technique followed by chemical-mechanical polishing with a mixed abrasive slurry consisting essentially of at least two inorganic metal oxide abrasive material particles at a pH below five, preferably on the order of 3.5 to 4.0, in order to control the polish rate selectivity of silicon dioxide to silicon nitride of the circuit and to reduce surface defects.

Abstract: An abrasive slurry for chemical-mechanical polishing, e.g. to planarize metal and silicon wafers employed in the fabrication of microelectric devices and the like, the slurry consisting essentially only of a mixture of at least two inorganic metal oxides to provide superior performance in properties such as improved oxide and metal polish rates, controlled polish rate selectivity, low surface defectivity and enhanced slurry stability over that obtainable with a single inorganic metal oxide abrasive material.