Patents by Inventor Arinobu NAKAMURA

Arinobu NAKAMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916365
    Abstract: A wiring substrate includes a first conductive plate, a second conductive plate, and a first insulator. A first end of an element is connected to a first main surface of the first conductive plate, and a second end of the element is connected to a first main surface of the second conductive plate. The first insulator includes a first portion and a second portion. The first portion separates the first conductive plate and the second conductive plate from each other. The second portion is continuous with the first portion, and covers at least a portion of the first main surface. The first portion includes an end portion. The end portion protrudes from the second main surface to the opposite of the first main surface or from the second main surface to the opposite of the first main surface.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: February 27, 2024
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Arinobu Nakamura
  • Publication number: 20230354526
    Abstract: An object of the present disclosure is to provide a technique with which it is possible to achieve a weight reduction in a circuit assembly that includes two semiconductor elements that constitute a bidirectional relay A circuit assembly includes: a first bus bar; a second bus bar; a first semiconductor element; a second semiconductor element; a power circuit portion that electrically connects a first power terminal of the first semiconductor element and a third power terminal of the second semiconductor element; and a control circuit portion for electrically connecting both a first signal terminal of the first semiconductor element and a second signal terminal of the second semiconductor element to a control apparatus. At least one of the power circuit portion and the control circuit portion includes a flexible conductive path.
    Type: Application
    Filed: August 3, 2021
    Publication date: November 2, 2023
    Inventors: Hideo MORIOKA, Arinobu NAKAMURA
  • Patent number: 11711887
    Abstract: An object of the present disclosure is to be able to further reduce the size of a substrate structure including a plurality of elements. The substrate structure includes: a base substrate that includes a first conductive plate and a second conductive plate; a first element connected to the first conductive plate and the second conductive plate; and a second element connected to the first conductive plate and the second conductive plate. The first conductive plate and the second conductive plate are disposed on the same plane on the base substrate in a state of being electrically insulated from each other, the first element is mounted on a first main surface of the base substrate, and the second element is mounted on a second main surface that is on the opposite side to the first main surface relative to the base substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 25, 2023
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura
  • Patent number: 11621503
    Abstract: Provided is a substrate unit including a case accommodating a circuit board; a bus bar electrically connected to the circuit board, and includes an extending portion extending out of the case; and an external thread portion for electrically connecting the extending portion to a connection terminal of a wire harness, the external thread portion including a shaft portion with an external thread, and a head portion that is noncircular, and protrudes at one end portion of the shaft portion in a radial direction of the shaft portion, wherein the case includes a fitting recess to which the head portion is fitted by sliding the external thread portion in a direction intersecting an axial direction of the external thread portion, and that has an abutment surface by which the head portion is stopped, and, at least on the two sides of the abutment surface, relief recesses that define a gap.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 4, 2023
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Koki Uchida, Arinobu Nakamura
  • Publication number: 20220361317
    Abstract: An object of the present disclosure is to be able to further reduce the size of a substrate structure including a plurality of elements. The substrate structure includes: a base substrate that includes a first conductive plate and a second conductive plate; a first element connected to the first conductive plate and the second conductive plate; and a second element connected to the first conductive plate and the second conductive plate. The first conductive plate and the second conductive plate are disposed on the same plane on the base substrate in a state of being electrically insulated from each other, the first element is mounted on a first main surface of the base substrate, and the second element is mounted on a second main surface that is on the opposite side to the first main surface relative to the base substrate.
    Type: Application
    Filed: May 28, 2020
    Publication date: November 10, 2022
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura
  • Patent number: 11445602
    Abstract: A power circuit includes bus bars that are connected to terminals of an FET and are provided flush with each other, and a first insulation region arranged between the bus bars. The power circuit includes a bus bar to which the FET is fixed, a conductive sheet that is connected to another bus bar via a first connection portion and electrically connects source terminals of the FET to the other bus bar, and a second connection portion that is provided in the conductive sheet and electrically connects the source terminals to the other bus bar.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 13, 2022
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura, Akira Haraguchi, Heng Cao
  • Publication number: 20220224096
    Abstract: A wiring substrate includes a first conductive plate, a second conductive plate, and a first insulator. A first end of an element is connected to a first main surface of the first conductive plate, and a second end of the element is connected to a first main surface of the second conductive plate. The first insulator includes a first portion and a second portion. The first portion separates the first conductive plate and the second conductive plate from each other. The second portion is continuous with the first portion, and covers at least a portion of the first main surface. The first portion includes an end portion. The end portion protrudes from the second main surface to the opposite of the first main surface or from the second main surface to the opposite of the first main surface.
    Type: Application
    Filed: April 22, 2020
    Publication date: July 14, 2022
    Inventor: Arinobu Nakamura
  • Patent number: 11343913
    Abstract: Provided is a circuit board structure including a first circuit board having bus bars and a second circuit board arranged spaced apart from the first circuit board, multiple FET being arranged on the bus bars, and terminals of the multiple FETs being connected to the bus bars. The circuit board structure includes a conducting wire group sheet that covers a portion of the bus bar and is provided with multiple conducting wires that allow electricity to flow between gate terminals of the FETs and the second circuit board. The semiconductor element FETs, which are arranged side by side, are provided such that the gates terminals are arranged in the same direction with respect to the direction in which the semiconductor element FETs are arranged side by side.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 24, 2022
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura, Akira Haraguchi
  • Publication number: 20220022337
    Abstract: A power circuit includes multiple bus bars that are connected to multiple terminals of an FET, are provided flush with each other, and are each insulated from each other. The power circuit includes one bus bar that is connected to drain terminals of the FET, a solder fixing portion of the FET that is arranged on the bus bar, and another bus bar that is connected to source terminals of the FET via a conductive connection sheet.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 20, 2022
    Inventors: Shungo Hiratani, Arinobu Nakamura, Shinsuke Okumi, Akira Haraguchi, Heng Cao
  • Publication number: 20210358852
    Abstract: A power circuit is provided with two bus bars in a single plane connected to terminals of a plurality of FETs and includes an insulating region interposed between the bus bars, the power circuit including: a first conductive piece to which one group of the plurality of FETs is fixed; a second conductive piece to which another group of the plurality of FETs is fixed, wherein the plurality of FETs are alternately fixed to the first conductive piece and the second conductive piece.
    Type: Application
    Filed: July 12, 2019
    Publication date: November 18, 2021
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura, Akira Haraguchi, Heng Cao
  • Publication number: 20210267058
    Abstract: Provided is a circuit board structure including a first circuit board having bus bars and a second circuit board arranged spaced apart from the first circuit board, multiple FET being arranged on the bus bars, and terminals of the multiple FETs being connected to the bus bars. The circuit board structure includes a conducting wire group sheet that covers a portion of the bus bar and is provided with multiple conducting wires that allow electricity to flow between gate terminals of the FETs and the second circuit board. The semiconductor element FETs, which are arranged side by side, are provided such that the gates terminals are arranged in the same direction with respect to the direction in which the semiconductor element FETs are arranged side by side.
    Type: Application
    Filed: July 12, 2019
    Publication date: August 26, 2021
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura, Akira Haraguchi
  • Publication number: 20210267048
    Abstract: A power circuit includes bus bars that are connected to terminals of an FET and are provided flush with each other, and a first insulation region arranged between the bus bars. The power circuit includes a bus bar to which the FET is fixed, a conductive sheet that is connected to another bus bar via a first connection portion and electrically connects source terminals of the FET to the other bus bar, and a second connection portion that is provided in the conductive sheet and electrically connects the source terminals to the other bus bar.
    Type: Application
    Filed: July 12, 2019
    Publication date: August 26, 2021
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura, Akira Haraguchi, Heng Cao
  • Publication number: 20210247243
    Abstract: Provided is a circuit board assembly including an electronic component that generates heat, and a thermistor that is mounted on a circuit board that is spaced apart from the electronic component and that detects the temperature of the electronic component. The circuit board assembly further includes a heat conductive pattern formed surrounding the thermistor, and a heat conductive member that conducts heat from the electronic component to the heat conductive pattern.
    Type: Application
    Filed: June 19, 2019
    Publication date: August 12, 2021
    Inventors: Shungo Hiratani, Hideaki Tahara, Arinobu Nakamura, Sanghee Chung
  • Patent number: 10869400
    Abstract: A case is provided with a drainage channel that smoothly drains water while also being able to suppress the intrusion of water into a housing space. The case includes a first case body in which a channel extending from a region serving as the housing space is formed. The channel includes a first channel portion having one end side connected to a first outlet and another end side connected to a second outlet, and a second channel portion connects the first channel portion and the housing space. Out of the opening edges of the second channel portion that face the first channel portion, a second-side opening edge, which is the edge on the second outlet side of the first channel portion, is located nearer to the housing space than a first-side opening edge, which is the edge on the first outlet side of the first channel portion, is.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: December 15, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Tahara, Kazuyoshi Ohara, Munsoku O, Arinobu Nakamura
  • Patent number: 10772194
    Abstract: A circuit board that includes a substrate that has an upper surface on which a circuit pattern is formed, and a lower surface to which a plurality of bus bars that are spaced apart are fixed; a placement through hole that extends through the upper surface and the lower surface and faces a bus bar of the plurality of bus bars and in which an electronic component is placed; and a terminal conductor foil that protrudes inward into the placement through hole from the lower surface and to which a terminal of the electronic component is connected.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: September 8, 2020
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Tou Chin, Arinobu Nakamura
  • Patent number: 10681826
    Abstract: Provided is a substrate unit that has a simple structure and is able to prevent water that has entered the inside from reaching a mounting surface of the substrate. The substrate unit includes: a substrate, a first casing member that supports the substrate, and a second casing member that is integrated into one piece with the first casing member and is provided on a mounting surface side of the substrate, wherein the second casing member is provided with a protruding portion that protrudes into a housing space that is defined by the first casing member and the second casing member and houses the substrate, and intersects a plane that extends along the mounting surface of the substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: June 9, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Hideaki Tahara, Kazuyoshi Ohara, Munsoku O, Arinobu Nakamura
  • Patent number: 10652994
    Abstract: Provided is a circuit assembly in which the mounting area of a substrate can be increased. A circuit assembly includes an electronic component having a plurality of terminals, a conductive member for supporting the electronic component (10), at least one of the terminals of the electronic component being electrically connected to the conductive member, and a substrate provided with a conductive pattern to which another terminal of the electronic component is electrically connected, in which the substrate is fixed to a surface of the conductive member that is opposite to a surface of the conductive member that supports the electronic component.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 12, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Arinobu Nakamura, Tou Chin
  • Patent number: 10609811
    Abstract: A conductor is placed on a first placement portion of a heat dissipation member with an insulation member interposed therebetween. An FET is electrically connected to the conductor. When current flows between the drain and the source of the FET, the FET generates heat. A second placement portion of a circuit board is placed on the conductor. The conductor and the insulation member are sandwiched between the first placement portion and the second placement portion. In the heat dissipation member, a first extension portion extends from the first placement portion, and in the circuit board, a second extension portion extends from the second placement portion. The first extension portion is located opposite to and is spaced apart from the second extension portion, and a microcomputer is placed on an upper surface of the second extension portion. The microcomputer outputs a control signal for turning the FET ON or OFF.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 31, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shungo Hiratani, Hideaki Tahara, Yuuichi Hattori, Akira Haraguchi, Jun Ikeda, Arinobu Nakamura
  • Publication number: 20200077509
    Abstract: A conductor is placed on a first placement portion of a heat dissipation member with an insulation member interposed therebetween. An FET is electrically connected to the conductor. When current flows between the drain and the source of the FET, the FET generates heat. A second placement portion of a circuit board is placed on the conductor. The conductor and the insulation member are sandwiched between the first placement portion and the second placement portion. In the heat dissipation member, a first extension portion extends from the first placement portion, and in the circuit board, a second extension portion extends from the second placement portion. The first extension portion is located opposite to and is spaced apart from the second extension portion, and a microcomputer is placed on an upper surface of the second extension portion. The microcomputer outputs a control signal for turning the FET ON or OFF.
    Type: Application
    Filed: March 19, 2018
    Publication date: March 5, 2020
    Inventors: Shungo Hiratani, Hideaki Tahara, Yuuichi Hattori, Akira Haraguchi, Jun Ikeda, Arinobu Nakamura
  • Patent number: 10582607
    Abstract: Provided is a circuit assembly including: a circuit board; a bus bar having a top face fixed to a bottom face of the circuit board; an electronic component disposed on a top face of the bus bar; a heat dissipation member disposed on a bottom face of the bus bar; a heat transfer member interposed between the bus bar and the heat dissipation member, to transfer heat of the bus bar to the heat dissipation member; and a screw extending through a stack of the circuit board and the bus bar, the screw screwed to the heat dissipation member, fixing the stack to the heat dissipation member; and a spacer interposed between the circuit board and the heat dissipation member, the spacer surrounding at least a portion of an outer circumference of a shaft portion of the screw, and maintaining a thickness of the heat transfer member substantially uniform.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: March 3, 2020
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Arinobu Nakamura, Tou Chin