Abstract: Methods and apparatus for calibrating signal processing chains using cross coupling between polarizations are described. Various exemplary methods and apparatus, in accordance with the present invention, are well suited for use in communications devices using beamforming and including arrays of TX/RX front ends, e.g., a first plurality of horizontal polarization front ends and a second plurality of vertical polarization front ends.

Abstract: Methods and apparatus for calibrating signal processing chains using cross coupling between polarizations are described. Various exemplary methods and apparatus, in accordance with the present invention, are well suited for use in communications devices using beamforming and including arrays of TX/RX front ends, e.g., a first plurality of horizontal polarization front ends and a second plurality of vertical polarization front ends.

Abstract: Controllable radio frequency power amplifiers (RFPAs), e.g., in a Hybrid-MIMO array, which are being driven at lower power levels, are operated at conditions such that their inherent EVM and ACLR are intentionally further increased. This increase of inherent EVM and ACLR is done in a precise manner, and the increased inherent EVM and ACLR are cancelled or reduced by the EVM and ACLR of the input Array DPD signal. The net result is improved EVM and ACLR performance over a broader range of angles. Exemplary methods and apparatus for increasing distortion include individual or combinations of: i) changing the DC bias a RFPA based on average operating power level; ii) changing supply voltage, e.g. Vcc, of a RFPA based on average operating power level, iii) adding a controllable non-linear element, such as a diode or varactor, at the input of the RFPA, based on the average operating power.

Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.

Abstract: Certain aspects of the present disclosure provide semiconductor variable capacitors. One example semiconductor variable capacitor generally includes a semiconductor region, a first insulator region disposed below the semiconductor region, a first non-insulative region disposed below the first insulator region, a second non-insulative region disposed adjacent to the semiconductor region, and a third non-insulative region disposed adjacent to the semiconductor region, wherein the semiconductor region is disposed between the second non-insulative region and the third non-insulative region. In certain aspects, the semiconductor variable capacitor may include a second insulator region disposed above the semiconductor region and a second semiconductor region disposed above the second insulator region.

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a first semiconductor region; a first non-insulative region disposed adjacent to a first lateral side of the first semiconductor region; a second non-insulative region disposed adjacent to a second lateral side of the first semiconductor region, the second lateral side being opposite to the first lateral side; a second semiconductor region disposed adjacent to a third lateral side of the first semiconductor region, the second semiconductor region and the first semiconductor region having at least one of different doping types or different doping concentrations; an insulative layer adjacent to a top side of the first semiconductor region; and a third non-insulative region, the insulative layer being disposed between the third non-insulative region and the first semiconductor region.

Abstract: A global navigation satellite system receiver with filter bypass mode for improved sensitivity is disclosed. In an aspect, an apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter. The apparatus also includes a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by an unrelated local transmitter are transmitted with a signal power that exceeds a selected threshold, and to couple the antenna to the bypass signal path during other time intervals.

Abstract: Techniques to implement a filter for a selected signal path by reusing a circuit component in an unselected signal path are disclosed. In an exemplary design, an apparatus includes first, second, and third circuits. The first circuit passes a first radio frequency (RF) signal to an antenna when a first signal path is selected. The second circuit passes a second RF signal to the antenna when a second signal path is selected. The third circuit is selectively coupled to the first circuit, e.g., via a switch. The first and third circuits form a filter for the second RF signal (e.g., to attenuate a harmonic of the second RF signal) when the second signal path is selected and the first signal path is unselected. The first circuit may include a series inductor, and the third circuit may include a shunt capacitor.

Abstract: Techniques for protecting a power amplifier (PA) are described. In an exemplary design, an apparatus includes (i) a PA module to amplify an input RF signal and provide an output RF signal and (ii) a protection circuit to control a transmitter gain to protect the PA module against high peak voltage. In an exemplary design, the protection circuit includes a set of comparators to quantize an analog input signal and provide digital comparator output signals used to adjust the transmitter gain. In another exemplary design, the protection circuit reduces and increases the transmitter gain with hysteresis. In yet another exemplary design, the protection circuit has faster response to rising amplitude than falling amplitude of the output RF signal. The hysteresis and/or the different rise and fall responses may allow the protection circuit to avoid toggling the transmitter gain under severe load mismatch and to handle time-varying envelope due to amplitude modulation.

Abstract: In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

Abstract: A diversity receiver capable of receiving a CDMA system (e.g., a W-CDMA system) and a TDMA system (e.g., a GSM system), with receive diversity for at least one system, is described. W-CDMA is often referred to as UMTS. In one design, the diversity receiver includes a first receiver for GSM and a second receiver for UMTS. The first receiver may be implemented with one receiver design, may be spec-compliant for GSM, and may also support UMTS. The second receiver may be implemented with another receiver design, may be spec-compliant for UMTS, and may also support GSM. The first receiver may include a lowpass filter having a bandwidth that is adjustable for GSM and UMTS. The second receiver may include a bandpass filter used to attenuate a transmit frequency range for UMTS. Each receiver may include circuit blocks that are used for both GSM and UMTS.

Abstract: In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Abstract: A tunable loadline is disclosed. In an exemplary embodiment, an apparatus includes an amplifier configured to output an amplified signal having a selected power level and a first impedance network coupled to receive the amplified signal at an input terminal and generate a first output signal having a first power level at a first output terminal. The first impedance network being configured to load the amplified signal to convert the selected power level to the first power level. The apparatus also includes a second impedance network configured to selectively receive the first output signal and generate a second output signal having a second power level at a second output terminal. The second impedance network being configured to combine with the first impedance network to load the amplified signal to convert the selected power level to the second power level.

Abstract: Exemplary embodiments are directed to an amplifier module which may comprise a transmit path including a first amplifier and a second amplifier. The exemplary amplifier module may further include a transformer coupled between the first amplifier and the second amplifier and switchably configured for coupling the first amplifier in series with the second amplifier in a first mode and coupling the first amplifier to bypass the second amplifier in a second mode.

Abstract: Tunable matching circuits for power amplifiers are described. In an exemplary design, an apparatus may include a power amplifier and a tunable matching circuit. The power amplifier may amplify an input RF signal and provide an amplified RF signal. The tunable matching circuit may provide output impedance matching for the power amplifier, may receive the amplified RF signal and provide an output RF signal, and may be tunable based on at least one parameter effecting the operation of the power amplifier. The parameter(s) may include an envelope signal for the amplified RF signal, an average output power level of the output RF signal, a power supply voltage for the power amplifier, IC process variations, etc. The tunable matching circuit may include a series variable capacitor and/or a shunt variable capacitor. Each variable capacitor may be tunable based on a control generated based on the parameter(s).

Abstract: A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.