Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers.

Abstract: Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided over the barrier layer. Solder bumps are formed over the oxidation prevention caps. The oxidation prevention caps inhibit oxidation of the barrier layer during fabrication of the bump assemblies.

Abstract: Techniques are described to furnish an IR suppression filter, or any other interference based filter, that is formed on a transparent substrate to a light sensor. In one or more implementations, a light sensor includes a substrate having a surface. One or more photodetectors are formed in the substrate. The photodetectors are configured to detect light and provide a signal in response thereto. An IR suppression filter configured to block infrared light from reaching the surface is formed on a transparent substrate. The light sensor may also include a plurality of color pass filters disposed over the surface. The color pass filters are configured to filter visible light to pass light in a limited spectrum of wavelengths to the one or more photodetectors. A buffer layer is disposed over the surface and configured to encapsulate the plurality of color pass filters and adhesion layer.

Abstract: Light sensor devices are described that have a glass substrate, which includes a lens to focus light over a wide variety of angles, bonded to the light sensor device. In one or more implementations, the light sensor devices include a substrate having a photodetector formed therein. The photodetector is capable of detecting light and providing a signal in response thereto. The sensors also include one or more color filters disposed over the photodetector. The color filters are configured to pass light in a limited spectrum of wavelengths to the photodetector. A glass substrate is disposed over the substrate and includes a lens that is configured to collimate light incident on the lens and to pass the collimated light to the color filter.

Abstract: Techniques are described to furnish an IR suppression filter that is formed on a glass substrate to a light sensor. In one or more implementations, a light sensor includes a substrate having a surface. One or more photodetectors are formed in the substrate and configured to detect light and provide a signal in response thereto. An IR suppression filter configured to block infrared light from reaching the surface is formed on a glass substrate. The light sensor also includes a plurality of color pass filters disposed over the surface. The color pass filters are configured to filter visible light to pass light in a limited spectrum of wavelengths to the one or more photodetectors. A buffer layer is disposed over the surface and configured to encapsulate the plurality of color pass filters and adhesion layer. The light sensor further includes through-silicon vias to provide electrical interconnections between different conductive layers.

Abstract: Embodiments of the invention generally relate to methods for treating a silicon-containing material on a substrate surface and performing a chamber clean process. In one embodiment, a method includes positioning a substrate containing a silicon material having a contaminant thereon within a process chamber and exposing the substrate to an etching gas containing chlorine gas and a silicon source gas while removing the contaminant and maintaining a temperature of the substrate within a range from about 500° C. to less than about 800° C. during an etching process. The method further includes exposing the substrate to a deposition gas after the etching process during a deposition process and exposing the process chamber to a chamber clean gas containing chlorine gas and the silicon source gas after the deposition process during a chamber clean process. The chamber clean process limits the etching of quartz and metal surfaces within the process chamber.

Abstract: Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 ? per minute to about 20 ? per minute during the etching process.

Abstract: In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about <100 ?/min). The silicon-containing surface is exposed to an etching gas that contains an etchant and a silicon source. Preferably, the etchant is chlorine gas so that a relatively low temperature (e.g., <800° C.) is used during the process. In another embodiment, a method for etching a silicon-containing surface during a fast etch process (e.g., about >100 ?/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. In another embodiment, a method for cleaning a process chamber is provided which includes exposing the interior surfaces with a chamber clean gas that contains an etchant and a silicon source.

Abstract: WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided over the barrier layer. Solder bumps are formed over the oxidation prevention caps. The oxidation prevention caps inhibit oxidation of the barrier layer during fabrication of the bump assemblies.

Abstract: Systems, methods, and apparatus are provided for using a cluster tool to pre-clean a substrate in a first processing chamber utilizing a first gas prior to epitaxial film formation, transfer the substrate from the first processing chamber to a second processing chamber through a transfer chamber under a vacuum, and form an epitaxial layer on the substrate in the second processing chamber without utilizing the first gas. Numerous additional aspects are disclosed.

Abstract: Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: A method of forming a planar waveguide structure, comprising forming a first graded layer on a substrate, wherein the first graded layer comprises a first and a second optical material, wherein the concentration of the first optical material increases with the height of the first graded layer; forming a second graded layer on the first graded layer, the second graded layer comprising the first and second optical materials wherein the concentration of the first optical material decreases with the height of the second graded layer. The method further including forming a uniform layer on the first graded layer, the uniform layer containing first and second optical materials wherein the first optical material concentration is constant.

Abstract: Methods and apparatus for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment of the epitaxial layer converts interstitial carbon to substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the treatment of the epitaxial layer involves annealing for short periods of time, for example, by laser annealing, millisecond annealing, rapid thermal annealing, and spike annealing in a environment containing nitrogen.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: The present invention provides systems, devices and methods for fabricating miniature low-power light sensors. With the present invention, a light sensitive component, such as a diode, is fabricated on the front side of a silicon wafer. Connectivity from the front side of the wafer to the back side of the wafer is provided by a through silicon via. Solder bumps are then placed on the back side of the wafer to provide coupling to a printed circuit board. The techniques described in the present invention may also be applied to other types of semiconductor devices, such as light-emitting diodes, image sensors, pressure sensors, and flow sensors.