Patents by Inventor Arun K. Nanda

Arun K. Nanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080082638
    Abstract: Providing reference tokens. A method includes receiving a request for a token. In response to the request for a token and in place of a token, one or more rich pointers are sent referencing one or more tokens. The rich pointers point to locations where one or more actual tokens can be retrieved. When only a single pointer is sent, the pointer is a reference other than an HTTP URL.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Applicant: MICROSOFT CORPORATION
    Inventors: Christopher G. Kaler, Arun K. Nanda
  • Publication number: 20080028215
    Abstract: A user interacts with a client containing personal identity information operable to identify the user to a relying party when the relying party is presented with claims comprising a portion of the personal identity information. The personal identity information includes one or more claims, metadata associated with the one or more claims, and backing data associated with the one or more claims. The user may initiate use of another client and seek to be identified by the relying party while interacting with the other client by first porting the personal identity information to the other client. Porting the personal identity information includes binding the personal identity information and sending the bound personal identity information to a receiving client.
    Type: Application
    Filed: July 28, 2006
    Publication date: January 31, 2008
    Applicant: Microsoft Corporation
    Inventors: Arun K. Nanda, Ruchita Bhargava, Lucas R. Melton
  • Patent number: 7290053
    Abstract: A system and method for managing the creation of objects in a distributed directory service system assigns quotas to entities (such as users, computers, groups) to limit the number of objects each entity is allowed to create and own. For purposes of enforcing the quotas, tombstones generated for deleted objects are taken into account in the calculation of a weighted total number of objects owned by an entity, with each tombstone counted as a configurable fraction of a regular object. When an entity requests a directory operation that will increase the number of objects owned by that entity, the number of system objects owned by that entity is added to the number of tombstones multiplied by the fractional tombstone factor to generate the weighted total, which is compared to the quota of that entity to determine when the requested operation should be performed.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: October 30, 2007
    Assignee: Microsoft Corporation
    Inventors: Arun K. Nanda, Donald J. Hacherl
  • Patent number: 7290052
    Abstract: A system and method for managing the creation of objects in a distributed directory service system assigns quotas to entities (such as users, computers, groups) to limit the number of objects each entity is allowed to create and own. For purposes of enforcing the quotas, tombstones generated for deleted objects are taken into account in the calculation of a weighted total number of objects owned by an entity, with each tombstone counted as a configurable fraction of a regular object. When an entity requests a directory operation that will increase the number of objects owned by that entity, the number of system objects owned by that entity is added to the number of tombstones multiplied by the fractional tombstone factor to generate the weighted total, which is compared to the quota of that entity to determine when the requested operation should be performed.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: October 30, 2007
    Assignee: Microsoft Corporation
    Inventors: Arun K. Nanda, Donald J. Hacherl
  • Publication number: 20070204325
    Abstract: A digital identity system includes a principal including an identity selector programmed to receive a security policy from a relying party, review a plurality of digital identities associated with the principal, and request one or more claims related to an identity of the principal from an identity provider. The principal is further programmed to receive one or more security tokens including the claims from the identity provider, and to forward the security tokens to the relying party.
    Type: Application
    Filed: July 28, 2006
    Publication date: August 30, 2007
    Applicant: Microsoft Corporation
    Inventors: Kim Cameron, Arun K. Nanda
  • Patent number: 7247556
    Abstract: A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: July 24, 2007
    Assignee: Agere Systems Inc.
    Inventors: Arun K. Nanda, Nace Rossi
  • Patent number: 7141486
    Abstract: A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: November 28, 2006
    Assignee: Agere Systems Inc.
    Inventors: Nace Rossi, Ranbir Singh, Arun K. Nanda
  • Patent number: 6702654
    Abstract: The present invention provides an improved conditioning wheel for conditioning polishing pads used to polish semiconductor wafers. In one embodiment, the conditioning wheel includes a planar body having a metal surface located thereon. The metal surface has abrasive particles embedded therein and a retainer coating deposited over the metal surface and the abrasive particles. The retainer coating inhibits the abrasive particles from dislodging during a conditioning process.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: March 9, 2004
    Assignee: Agere Systems Inc.
    Inventors: Arun K. Nanda, Jose Omar Rodriguez, Laurence D. Schultz, Charles A. Storey
  • Patent number: 6436829
    Abstract: The present invention provides a method for polishing a semiconductor substrate comprising: (a) polishing a metal layer located on a semiconductor wafer with a slurry at a first polishing rate, wherein the slurry has a predetermined concentration of an oxidizing agent therein; (b) forming a diluted slurry by diluting the polishing slurry with a diluent to substantially reduce the predetermined concentration of the oxidizing agent; and (c) polishing the metal layer at a second polishing rate less than the first polishing rate and in the presence of the diluted slurry.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: August 20, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Nace Layadi, Arun K. Nanda
  • Publication number: 20020106829
    Abstract: The present invention provides an improved conditioning wheel for conditioning polishing pads used to polish semiconductor wafers. The conditioning wheel includes a planar body and a homogeneous abrasive layer located on the planar body wherein the homogenous abrasive layer includes abrasive protrusions comprised of a same material as the homogenous abrasive layer.
    Type: Application
    Filed: February 6, 2001
    Publication date: August 8, 2002
    Inventors: Arun K. Nanda, Jose Omar Rodriguez, Laurence D. Schultz, Charles A. Storey
  • Publication number: 20020106979
    Abstract: The present invention provides an improved conditioning wheel for conditioning polishing pads used to polish semiconductor wafers. In one embodiment, the conditioning wheel includes a planar body having a metal surface located thereon. The metal surface has abrasive particles embedded therein and a retainer coating deposited over the metal surface and the abrasive particles. The retainer coating inhibits the abrasive particles from dislodging during a conditioning process.
    Type: Application
    Filed: February 7, 2001
    Publication date: August 8, 2002
    Inventors: Arun K. Nanda, Jose Omar Rodriguez, Laurence D. Schultz, Charles A. Storey
  • Patent number: 6153452
    Abstract: Methods of manufacturing a semiconductor device. One method includes the steps of: (1) providing a substrate over which is to be deposited a metal silicide layer having a stoichiometric ratio within a desired range, (2) providing a target composed of a metal silicide, the target subject to degradation by reason of use, (3) sputtering atoms from the target to form the metal silicide layer over the substrate, the stoichiometric ratio subject to being without the desired range by reason of the degradation of the target and (4) depositing a predetermined amount of silicon on the metal silicide layer to return the stoichiometric ratio to within the desired range, a useful life of the target thereby increased.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: November 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Sailesh M. Merchant, Arun K. Nanda, Pradip K. Roy, Hem M. Vaidya
  • Patent number: 6140211
    Abstract: A method for recycling a used silicon wafer on which ICs have been formed by IC fabrication equipment comprised of first grinding the wafer using a coarse grinding apparatus and then grinding the wafer suing a fine grinding apparatus. The coarse grinding apparatus and the fine grinding apparatus are identical to one another except for the nature of the respective grinding they perform. Deionized water is used during both grinding processes to reduce friction and to control dust. The used wafer is first mounted on a chuck of the coarse grinding apparatus that rotates at a first predetermined speed. A diamond wheel mounted on a grinding wheel holder of the coarse grinding apparatus rotates at a second predetermined speed that is faster than the first speed. The rotating wheel and the rotating wafer are brought into contact with one another and the wafer is ground until a predetermined amount of semiconductor material is removed from the face of the wafer.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: October 31, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Arun K. Nanda, Jose O. Rodriguez
  • Patent number: 6056630
    Abstract: The present invention provides a unique polishing apparatus, such as a chemical/mechanical polishing apparatus, that includes a pivoting apparatus having a first end coupled to a carrier head and a second end coupled to a rotatable shaft wherein the pivoting apparatus is configured to exert a pivoting force with respect to the carrier head to pivot the carrier head with respect to the rotatable shaft to more easily break the surface tension formed by the slurry during the polishing process. This system provides a polishing apparatus that can reduce the amount of semiconductor wafer breakage associated with present processes and apparatus.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: May 2, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Arun K. Nanda, Laurence D. Schultz
  • Patent number: 6051500
    Abstract: The present invention provides a method for polishing a semiconductor substrate having a first layer of material formed on a second layer of different material. In one embodiment, the method includes placing the semiconductor substrate against a polishing surface and polishing the semiconductor substrate, producing a first vibration by polishing and removing the first layer, producing a second vibration by polishing at least a portion of the second layer, and detecting a change from the first vibration to the second vibration with a vibration sensor. The vibration that is sensed in the present invention is physical or mechanical vibration, and it is not a vibration associated with a change in temperature. The vibration sensor may be of varying types. For example, the vibration sensor may be an acoustic sensor or an ultrasonic sensor.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: April 18, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Alvaro Maury, Arun K. Nanda, Omar Rodriguez
  • Patent number: 5599739
    Abstract: Tungsten plugs are formed by passivating a substrate having a contact hole with SiH.sub.4, forming a nucleation layer on the passivated substrate by reducing WF.sub.6 with SiH.sub.4 at relatively low pressures and depositing tungsten to substantially fill the contact hole by reducing WF.sub.6 with H.sub.2 at relatively high pressures. Alternatively, rapid thermal annealing is used to cure pinhole defects in a titanium nitride layer on a substrate to avoid the formation of unwanted tungsten volcanoes.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: February 4, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Sailesh M. Merchant, Arun K. Nanda, Pradip K. Roy
  • Patent number: 5561083
    Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems. The selection of the thickness of the second sublayer to be a major portion and the inclusion of barrier layers are also described.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: October 1, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: Cheryl A. Bollinger, Edward A. Dein, Sailesh M. Merchant, Arun K. Nanda, Pradip K. Roy, Cletus W. Wilkins, Jr.
  • Patent number: 5523259
    Abstract: In an integrated circuit, an opening (e.g., via or window) is filled with an Al-based plug which has essentially a <111> orientation and comprises at most three grains. These characteristics are achieved by first depositing a texture control Ti layer having substantially a (002) basal plane orientation followed by at least three Al-based sublayers. The grain sizes and deposition conditions are controlled in such a way that during deposition of the third sublayer, the microstructure of the plug adjusts itself to produce a single grain (or at most three).
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: June 4, 1996
    Assignee: AT&T Corp.
    Inventors: Sailesh M. Merchant, Arun K. Nanda, Pradip K. Roy
  • Patent number: 5489552
    Abstract: Tungsten plugs are formed in a manner which avoids the formation of unwanted tungsten volcanoes by depositing at least three and preferably five to seven layers of tungsten within a contact hole to form a layered plug. In particularly useful embodiments, the layers are deposited at alternating fast and slow rates of deposition.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: February 6, 1996
    Assignee: AT&T Corp.
    Inventors: Sailesh M. Merchant, Arun K. Nanda, Pradip K. Roy
  • Patent number: 5441616
    Abstract: A method for forming an anti-reflective coating useful in the fabrication of integrated circuits is discussed. Applicants have found that preheating semiconductor wafers prior to the application of amorphous silicon anti-reflective coatings tends to reduce undesirable particulates which may attach to the wafer. The process is illustratively performed in a Varian 3180 machine having four stations. Illustratively, the wafer may be preheated between 70.degree. C. and 175.degree. C. prior to and during the sputter deposition of an amorphous silicon anti-reflective coating.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: August 15, 1995
    Assignee: AT&T Corp.
    Inventors: Arun K. Nanda, Mark J. Sundahl, Edward J. Vajda