Abstract: Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.

Abstract: A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

Abstract: A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

Abstract: In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

Abstract: Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.

Abstract: Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.

Abstract: A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

Abstract: In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

Abstract: Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.

Abstract: A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.

Abstract: An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

Abstract: A method and apparatus are used to process a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information. Command bits are set over a serial port input pin, and include at least one pointer bit indicative of a selected logical channel. In response to the command bits, the serial port controller sends signals indicative of the physical channel and the converter property specified in the selected logical channel to the ADC components.

Abstract: A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.

Abstract: A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Abstract: A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Abstract: In a signal processing integrated circuit having a plurality of physical channels and a plurality of gain registers, a plurality of offset registers and an plurality of setup registers, mechanisms are provided to assign one of a plurality of gain registers independently of a selected one of a plurality of offset registers when processing signals from a physical channel.

Abstract: A method and apparatus are used to continuously convert a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information for controlling the ADC components to produce a digital sample of the analog signal on the specified physical channel. At least one looping bit and at least one depth bit are also stored in a register on the serial port. The depth bit indicates a number of logical channels in one data scan. At least that number of logical channels are stored in the register. In response to a command bit indicating conversion mode, a quantity of data scans is output on a serial output pin of the serial port interface.

Abstract: A self-timed multiplier and method are disclosed together with an analog to digital converter (ADC), which reduces ADC latency without requiring large silicon areas for implementation. The self-timed multiplier may be utilized by delta-sigma ADCs to perform gain compensation multiplications at the end of convolution, or may be used by other ADC designs or ADC systems for multiplications required during each convolution. The self-timed multiplier utilizes cascaded adders that produce completion signals to isolate the operation of the self-timed multiplier from the system clock of the ADC. The multiplier disclosed provides a self-timed, asynchronous circuit that will complete the desired multiplication in the time it takes for the required additions to propagate through the cascaded adders.

Abstract: A novel serial port interface system and method are disclosed. The serial port interface system achieves a three-pin interface mode with only a serial data input pin, a serial data output pin, and a serial clock pin by allocating a bit in an on-chip register to identify a three-pin conversion-done mode. In this three-pin mode, the serial data output pin signals an external device that data is ready to be accessed. Also disclosed with this three-pin conversion-done mode is a single conversion data read and a continuous conversion data read that may be selected through two separate bits in an on-chip register. In another aspect, a multiple register access capability is disclosed that allows multiple on-chip registers to be accessed with a single read/write command. This is accomplished by allocating a register select address in a command register to identify a group of registers, such as all of the set-up registers (gain, offset and configuration).