Patents by Inventor Ashish Pandya

Ashish Pandya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080133285
    Abstract: Our invention is a secure air travel system and method that eliminates security risks associated with passenger baggage by not allowing checked baggage and most carry-on baggage on the airliners that carry passengers. This method creates a two separate classes of air carriers or two classes of air carrier flights. One class transports passengers only and the other class transports only luggage of passengers between various locations. By eliminating the checked bags and most carry-on bags on the passenger-only flights, the security risks from weapons, bombs or other hazardous materials on these bags are totally eliminated from passenger-only flights. This mode of air travel can be implemented to co-exist with the current airlines and air travel methods.
    Type: Application
    Filed: January 4, 2008
    Publication date: June 5, 2008
    Inventors: Ashish A. Pandya, Alpa Pandya
  • Patent number: 7376755
    Abstract: A TCP/IP processor and data processing engines for use in the TCP/IP processor is disclosed. The TCP/IP processor can transport data payloads of Internet Protocol (IP) data packets using an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a TCP/IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: May 20, 2008
    Inventor: Ashish A. Pandya
  • Publication number: 20060136570
    Abstract: A runtime adaptable search processor is disclosed. The search processor provides high speed content search capability to meet the performance need of network line rates growing to 1 Gbps, 10 Gbps and higher. he search processor provides a unique combination of NFA and DFA based search engines that can process incoming data in parallel to perform the search against the specific rules programmed in the search engines. The processor architecture also provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported.
    Type: Application
    Filed: December 30, 2005
    Publication date: June 22, 2006
    Inventor: Ashish Pandya
  • Publication number: 20050108518
    Abstract: A runtime adaptable security processor is disclosed. The processor architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A high performance content search and rules processing security processor is disclosed which may be used for application layer and network layer security. A scheduler schedules packets to packet processors for processing.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 19, 2005
    Inventor: Ashish Pandya
  • Publication number: 20040210320
    Abstract: A runtime adaptable protocol processor is disclosed. The processor architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. Further, a runtime adaptable processor is coupled to the protocol processing hardware and may be dynamically adapted to perform hardware tasks as per the needs of the network traffic being sent or received and/or the policies programmed or services or applications being supported. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions.
    Type: Application
    Filed: May 12, 2004
    Publication date: October 21, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040165588
    Abstract: An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 26, 2004
    Inventor: Ashish A. Pandya
  • Patent number: 6773872
    Abstract: The present invention provides polymers which are substantially or completely free of inorganic contaminants and the use of such polymers as a resin component for photoresist compositions, particularly chemically-amplified positive-acting resists. Polymers of the invention also are suitable for use as a resin component for antireflective coating compositions (ARCs). More particularly, the invention provides methods for reducing such contaminants in polymerization initiators, particularly free radical initiators.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: August 10, 2004
    Assignee: Shipley Company, L.L.C.
    Inventors: Dana A. Gronbeck, Suzanne Coley, Chi Q. Truong, Ashish Pandya
  • Patent number: 6770413
    Abstract: The present invention relates to new copolymers and use of such copolymer as a resin binder component for photoresist compositions, particularly chemically-amplified positive-acting resists. Polymers of the invention include repeat units of 1) meta-hydroxystyrene groups, 2) para-hydroxystyrene groups, and 3) photoacid-labile groups.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: August 3, 2004
    Assignee: Shipley Company, L.L.C.
    Inventors: Hiroshi Ito, Ashish Pandya, Roger F. Sinta
  • Publication number: 20040037299
    Abstract: Disclosed are systems employing an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol processing and may also perform packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
    Type: Application
    Filed: June 10, 2003
    Publication date: February 26, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040037319
    Abstract: A TCP/IP processor and data processing engines for use in the TCP/IP processor is disclosed. The TCP/IP processor can transport data payloads of Internet Protocol (IP) data packets using an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a TCP/IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
    Type: Application
    Filed: June 10, 2003
    Publication date: February 26, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040030770
    Abstract: An IP Storage processor and processing engines for use in the IP storage processor is disclosed. The IP Storage processor uses an architecture that may provide capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also perform packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache may store a transport protocol session information database and/or store a storage information session database, for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
    Type: Application
    Filed: June 10, 2003
    Publication date: February 12, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040030757
    Abstract: An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol Layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.
    Type: Application
    Filed: June 10, 2003
    Publication date: February 12, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040030806
    Abstract: A memory system for a high performance IP processor is disclosed. The memory system allows the architecture for an IP processor that may provide capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also perform packet inspection through Layer 7. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
    Type: Application
    Filed: June 10, 2003
    Publication date: February 12, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040010545
    Abstract: Disclosed are systems employing an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol processing and may also perform packet inspection through Layer 7. A set of engines may perform passthrough packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 15, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20040010612
    Abstract: An architecture provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 15, 2004
    Inventor: Ashish A. Pandya
  • Publication number: 20030207200
    Abstract: The present invention relates to new polymers that contain repeat units of phenol and photoacid-labile esters that contain an alicyclic group, preferably a bulky group that suitably may contain 7 to about 20 carbons, such as an alkyladamantyl, ethylfencyl, tricyclo decanyl, or pinanyl group. Polymers of the invention are useful as a component of chemically-amplified positive-acting resists.
    Type: Application
    Filed: December 6, 2002
    Publication date: November 6, 2003
    Applicant: Shipley Company, L.L.C.
    Inventors: George G. Barclay, Ashish Pandya, Wang Yueh, Anthony Zampini, Gary Ganghui Teng, Zhibiao Mao
  • Publication number: 20030141411
    Abstract: Our invention is a secure air travel system and method that eliminates security risks associated with passenger baggage by not allowing checked baggage and most carry-on baggage on the airliners that carry passengers. This method creates a two separate classes of air carriers or two classes of air carrier flights. One class transports passengers only and the other class transports only luggage of passengers between various locations. By eliminating the checked bags and most carry-on bags on the passenger-only flights, the security risks from weapons, bombs or other hazardous materials on these bags are totally eliminated from passenger-only flights. This mode of air travel can be implemented to co-exist with the current airlines and air travel methods.
    Type: Application
    Filed: April 12, 2002
    Publication date: July 31, 2003
    Inventors: Ashish Pandya, Alpa Pandya
  • Patent number: 6492086
    Abstract: The present invention relates to new polymers that contain repeat units of phenol and photoacid-labile esters that contain an alicyclic group, preferably a bulky group that suitably may contain 7 to about 20 carbons, such as an alkyladamantyl, ethylfencyl, tricyclo decanyl, or pinanyl group. Polymers of the invention are useful as a component of chemically-amplified positive-acting resists.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: December 10, 2002
    Assignee: Shipley Company, L.L.C.
    Inventors: George G. Barclay, Ashish Pandya, Wang Yueh, Anthony Zampini, Gary Ganghui Teng, Zhibiao Mao
  • Publication number: 20020142246
    Abstract: The present invention provides polymers which are substantially or completely free of inorganic contaminants and the use of such polymers as a resin component for photoresist compositions, particularly chemically-amplified positive-acting resists. Polymers of the invention also are suitable for use as a resin component for antireflective coating compositions (ARCs). More particularly, the invention provides methods for reducing such contaminants in polymerization initiators, particularly free radical initiators.
    Type: Application
    Filed: December 27, 2001
    Publication date: October 3, 2002
    Applicant: Shipley Company, L.L.C.
    Inventors: Dana A. Gronbeck, Suzanne Coley, Chi Q. Truong, Ashish Pandya
  • Publication number: 20020012869
    Abstract: The invention provides novel cross-linked polymers and positive chemically-amplified photoresist compositions that comprise a photoactive component and such crosslinked polymers. Resists of the invention can exhibit enhanced lithographic results relative to comparable compositions where the polymers are not crosslinked.
    Type: Application
    Filed: February 9, 2001
    Publication date: January 31, 2002
    Applicant: Shipley Company, L.L.C.
    Inventors: Timothy G. Adams, Martha M. Rajaratnam, Ashish A. Pandya, Roger F. Sinta, Pushkara R. Varanasi, Kathleen Cornett, Ahmad D. Katnani