Abstract: A storage system includes a storage unit having routing circuits networked with each other, each of the routing circuits configured to route packets to node modules that are connected thereto, each of the node modules including nonvolatile memory, and connection units, each coupled with one or more of the routing circuits for communication therewith, and configured to access each of the node modules through one or more of the routing circuits. When a first connection unit transmits to a target node module a lock command to lock a memory region of the target node module for access thereto, and then a second connection unit transmits a write command to the target node module before the first connection unit transmits to the target node module an unlock command to unlock the memory region, the target node module is configured to return an error notice to the second connection unit.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.

Abstract: According to one embodiment, a storage device includes a processing unit and a plurality of storage units. The processing unit includes a processor and a network communication unit. The storage unit includes a processor input/output port connected to the processing unit via a bus, a storage-unit input/output port connected to adjacent storage unit thereto, a memory capable of storing data, and a routing unit configured to perform a transfer process by determining a transfer route of the data to another one of the storage units on the basis of positional information of the storage unit included in the data.

Abstract: According to one embodiment, a storage system includes a storage which includes a plurality of node memories including a nonvolatile memory and a control unit which controls the nonvolatile memory, a routing unit which controls packet transfer between two or more of the node memories, and a packet control unit which analyzes the packet transferred from the routing unit.

Abstract: According to one embodiment, a storage system includes a plurality of memory units including a nonvolatile memory and a control unit which controls the nonvolatile memory, a routing unit which controls transfer of a packet between the memory units. The routing unit uses a partial address described in the packet and not the full address.

Abstract: According to one embodiment, a storage system includes a storage which includes a plurality of node memories including a nonvolatile memory and a control unit which controls the nonvolatile memory and a routing unit which controls packet transfer between two or more of the node memories, a connection unit which connects the storage unit to outside and controls the storage unit, and a management unit which at least monitors power supply voltages of the storage and the connection unit.

Abstract: A storage device according to an embodiment includes a plurality of memory nodes and a first connection unit. Each memory node includes nonvolatile memory and is connected to each other in two or more different directions. The first connection unit adds a first lifetime to a command which is externally supplied, and transmits the command including the first lifetime to a first memory node. A second memory node having received the command among the plural memory nodes, if the second memory node is not a destination of the command, subtracts the first lifetime added to the first command. The second memory node discards the command after the subtraction when the first lifetime after the subtraction is less than a threshold. The second memory node transfers the command after the subtraction to the adjacent memory node when the first lifetime after the subtraction is larger than the threshold.

Abstract: According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.

Abstract: According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.

Abstract: A distributed computing system includes a group of interconnected memory nodes, where one of the memory nodes is configured as a transaction ID manager. The transaction ID manager is configured to manage concurrency of database transactions by issuing a transaction ID for each database transaction performed in the system. In some embodiments, each memory node in the two-dimensional matrix is configured as a transaction ID manager. In such embodiments, the unique transaction IDs generated by the transaction ID manager at each memory node are transmitted with node-specific information, so that the unique transaction IDs generated at each memory node are distinguished from the unique transaction IDs generated by other memory nodes.

Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.

Abstract: A storage system includes a memory unit group that includes a first memory unit and a plurality of second memory units, and the first memory unit is connected to the plurality of second memory units so that data can be transmitted between the first memory unit and the second memory units. The plurality of second memory units is mounted on a same first substrate. One second memory unit of the plurality of second memory units cooperates with the first memory unit and does not cooperate with the other second memory units of the plurality of second memory units.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

Abstract: According to an embodiment, a semiconductor memory device includes a controller and a second storage unit. The controller is configured to control a write process of writing data into a first storage unit in which data supplied from a host device are stored or a read process of reading the data stored in the first storage in response to a request from the host device. The second storage unit is temporarily used in the write process or the read process. The second storage unit includes a nonvolatile third storage unit having an area for storing a duplicate of the data to be written by the write process; and a nonvolatile fourth storage unit having a work area for the write process or the read process and having a higher read/write speed than the third storage unit.

Abstract: According to one embodiment, a storage system includes a plurality of memory nodes that are connected to each other in a plurality of different directions. Each memory node stores a count value. Each memory node, when receiving an update command of which destination is not own memory node, transmits the update commando to other memory nodes connected thereto. Each memory node, when receiving an update command of which destination is own memory node, executes the update command, increases the stored count value, and issues a notice indicating the increased count value.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

Abstract: According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1. Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.

Abstract: A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.