Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.

Abstract: According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

Abstract: A storage device according to an embodiment includes a plurality of memory nodes and a first connection unit. Each memory node includes nonvolatile memory and is connected to each other in two or more different directions. The first connection unit adds a first lifetime to a command which is externally supplied, and transmits the command including the first lifetime to a first memory node. A second memory node having received the command among the plural memory nodes, if the second memory node is not a destination of the command, subtracts the first lifetime added to the first command. The second memory node discards the command after the subtraction when the first lifetime after the subtraction is less than a threshold. The second memory node transfers the command after the subtraction to the adjacent memory node when the first lifetime after the subtraction is larger than the threshold.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

Abstract: According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

Abstract: In general, according to one embodiment, a DA converter configured to convert a digital signal comprising n (n>1) bits to an analog current to output the analog current from an output terminal, includes n voltage-current converters. Each of them corresponds to each bit of the digital signal and is configured to generate a current depending on the corresponding bit. A k-th (k is an integer of 0 to n?1) voltage-current converter includes a first transistor whose threshold voltage is adjustable. The first transistor includes a semiconductor substrate, a first diffusion region, a second diffusion region, an insulating film, a charge accumulating film, and a gate.

Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

Abstract: A semiconductor device includes a semiconductor substrate, a source region, a drain region, an insulating film and a gate electrode. The source region is formed in the semiconductor substrate. The drain region is formed in the semiconductor substrate and being separate from the source region. The insulating film is formed between the source region and the drain region and on or above the semiconductor substrate. The insulating film includes lanthanum aluminate containing at least one element selected from Si, Ge, Mg, Ca, Sr, Ba and N. The lanthanum aluminate contains at least one element selected from Ti, Hf and Zr. The gate electrode is formed on the insulating film.

Abstract: According to an embodiment, a storage device includes a plurality of memory nodes and a control unit. Each of the memory nodes includes a storage unit including a plurality of storage areas having a predetermined size. The memory nodes are connected to each other in two or more different directions. The memory nodes constitute two or more groups each including two or more memory nodes. The control unit is configured to sequentially allocate data writing destinations in the storage units to the storage areas respectively included in the different groups.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.

Abstract: According to one embodiment, a storage device includes a processing unit and a plurality of storage units. The processing unit includes a processor and a network communication unit. The storage unit includes a processor input/output port connected to the processing unit via a bus, a storage-unit input/output port connected to adjacent storage unit thereto, a memory capable of storing data, and a routing unit configured to perform a transfer process by determining a transfer route of the data to another one of the storage units on the basis of positional information of the storage unit included in the data.

Abstract: It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.

Abstract: According to one embodiment, a storage device includes an interface, a first and second memory blocks and a controller. The interface receives a content search request. The first memory block stores files and inverted files corresponding to contents included in the files. The second memory block stores a file search table. The controller creates the inverted file for each content included in the files and stores IDs of the files including the content in the inverted file. The controller obtains, by search of the content, a corresponding inverted file from the inverted files stored in the first memory block and stores, in the file search table, the IDs of the files included in the obtained inverted file. The controller outputs the IDs of the files stored in the file search table from the interface as a search result for the content search request.

Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

Abstract: According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

Abstract: According to an embodiment, a mixer circuit includes first transistors each having a charge storage layer, a second transistor, a group of first nodes, and an output node. The first transistors as a pair receive a differential signal having a first frequency. The second transistor receives a signal having a second frequency. The group of first nodes makes the charge storage layer of at least any one of the first transistors store charge during non-operation period during which the differential signal having the first frequency and the signal having the second frequency are not mixed and reduces loss of the charge during operation period during which those signals are mixed, to adjust a threshold voltage of at least any one of the first transistors from outside. The output node outputs a signal resulting from mixing the differential signal having the first frequency and the signal having the second frequency.

Abstract: According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si1-xGex (0?x<0.5) with a crystal orientation perpendicular to the surface set to the [110] direction on the surface, forming source/drain regions and forming insulating films on side portions of the dummy gate. Next, the dummy gate is etched with using the insulating films as a mask, and a surface portion of the substrate between the source/drain regions is further etched. Next, a channel region formed of a III-V group semiconductor or Ge is grown between the source/drain regions by using the edge portions of the source/drain regions as seeds. Then, a gate electrode is formed above the channel region via a gate insulating film.

Abstract: A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.