Abstract: A semiconductor integrated circuit for a CMOS microcomputer and others having an analog circuit, in which a gate voltage of a transistor for setting a bias current is generated by arranging a diode formed by two islands in a MOS structure and a transistor in series, so as to decrease also a temperature dependence characteristic of the analog circuit. Thereby, the fluctuation of the characteristic of the analog circuit can be restrained despite of fluctuation not only of a power-supply voltage but also of a temperature.

Abstract: An intrinsic cipher code peculiar to each IC card is written and stored in EEPROM serving as a writable non-volatile memory in an IC card, as well as a routine for performing collation with the intrinsic cipher code before a test program is executed being stored in a read-only memory as to allow access to the test program when agreement is established. An attempt can thus be made to improve security for access to the test program.

Abstract: A non-contact IC card includes a data transmission/reception circuit for data exchange between the IC card and an external device; a data processor connected to the data transmission/reception circuit; a reset signal receiving circuit for receiving a reset signal from the external device and an initializing circuit for initializing the data processor on the basis of the reset signal received by the reset signal receiving circuit.

Abstract: A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus.

Abstract: A microcomputer comprises EEPROM provided as a fixed storage unit and a CPU for controlling the operation of the EEPROM, in which the EEPROM contains a divider which divides a stable clock signal from the outside of the microcomputer and converts it to a clock signal with a desired frequency, the clock signal is used as a synchronizing signal necessary for the writing data into the EEPROM. The CPU controls the operation of the EEPROM and sets the dividing ratio of the divider contained in the EEPROM at a desired value in accordance with the assignment from the outside of the microcomputer.

Abstract: An IC card with a product test program contained therein is provided with a read-only memory. This read-only memory stores various routines, and is arranged such that if a secret code assigned exclusively to that IC card has been already written in a non-volatile memory in the IC card, an externally entered secret code is collated with the stored secret code, and, if the collation is successful, the non-volatile memory is initialized. The test program can be executed only after the initialization has been completed.

Abstract: A microprocessor system including an EEPROM with a page mode writing function that prevents writing of erroneous data. The circuit includes a memory cell array divided into a plurality of pages each having a predetermined number of bytes, a data latch for latching bytes corresponding to a page, an exterior write control circuit which enables the data latch in response to a signal from the CPU to latch a sequence of bytes corresponding to a page, and an interior write control circuit which enables the memory cell array so that the bytes latched in the data latch are transferred therefrom to a page of the memory cell array. The exterior write control circuit includes a time measurement circuit and an interior write suppression circuit. The time measurement circuit measures the time which elapses from the initiation of the latching of bytes into the data latch, and outputs an overflow signal when the measured time exceeds a predetermined limit.

Abstract: An IC card includes an addressable CPU having a memory space including a special area including a first plurality of memory addresses which are addressable with a short instruction word, first and second memories in which test and application programs are stored, respectively, a bus which connects the CPU and the first and second memories, a first selection circuit for forming a first memory mapping arrangement in which at least a portion of the first memory is superimposed on the special area, a second selection circuit for forming a second memory mapping arrangement in which at least a portion of the second memory is superimposed on the special area, a detection circuit for detecting the execution of the test program or the application program, and a changeover circuit arranged to selectively operate the first and second selection circuits according to the result of detection executed by the detection circuit.

Abstract: An IC card has a CPU, a first memory for storing a test program, a second memory for storing an application progam, a bus connecting the CPU and the first and second memories. A detection circuit for detecting whether the CPU has began executing the application program stored in the second memory, and a disconnection circuit for disconnecting the first memory from the bus when the detection circuit detects that the CPU has begun executing the application program. The above-described arrangement makes it impossible to access the test program in the system ROM from the application program thereby preventing the occurrence of incorrect access.

Abstract: A memory device for detecting and correcting errors in stored data includes a circuit for generating an error-detection/correction code with respect to data to be stored, a memory cell array in which the data and the error-detection/correction code are stored, an error-detection/correction circuit for detecting and corrrecting errors in the data by using the error-detection/correction code when the data is read out of the memory cell array, and a function test circuit selectively and directly connected to the error-detection/correction circuit for testing the error-detection/correction circuit.