Patents by Inventor Atsushi Kaneko

Atsushi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8787022
    Abstract: According to one embodiment, coupling capacitance in a state in which a first heat radiation member is arranged between parallel flat plates of a first capacitor formed by a surface of a housing opposed to one surface of a printed circuit board and the printed circuit board is smaller than coupling capacitance in a state in which an integrally formed object having a relative dielectric constant of 5.8 is arranged between the first capacitor to cover a first radiating region containing the controller and the first nonvolatile semiconductor memories.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takakatsu Moriai, Toyokazu Eguchi, Atsushi Kaneko, Atsushi Okada
  • Publication number: 20140132966
    Abstract: An image reading device includes a transporter transporting a document to a reading position, a first corrector correcting a skew of the document by coming into contact with a leading edge thereof, a radiating unit radiating light to the document, an image-information acquiring unit acquiring image information of the document based on information of light reflected therefrom, a reflector reflecting the radiated light, a leading-edge detector comparing a quantity of light reflected by the reflector with a quantity of light reflected by the document so as to detect the leading edge, a skew-amount calculator calculating a skew amount of the leading edge, and a second corrector correcting a skew of the image information based on the skew amount. The device switches between the skew correction by the first corrector and the skew correction by the second corrector based on document information, the skew amount, or user's selection.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Shinji MASAKI, Atsushi KANEKO, Hiromi KITA, Kenji YAMADA, Nobutoshi HAMASAKI, Nobuyuki MARUNO
  • Publication number: 20140075100
    Abstract: A memory system includes a non-volatile memory having a physical memory region and a controller for conducting data transmission between the non-volatile memory and a host. The controller includes a section management module and a wear leveling module. The section management module divides the physical memory region into multiple sections including a first section and one or more of second sections. The wear leveling module performs independent wear leveling for each of the second sections without performing wear leveling for the first section. The section management module performs expansion of the first section according to a physical memory region expansion request from the host.
    Type: Application
    Filed: March 6, 2013
    Publication date: March 13, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi KANEKO, Masahiro TAMURA, Hiroshi NISHIMURA, Yasuo KUDO
  • Patent number: 8665504
    Abstract: A digital holography device includes a light source that emits light, the light source being provided for supply of object light beams formed by radiation, transmission, scattering, reflection, or diffraction of the emitted light from a subject, an array device that splits the light emitted from the light source into two kinds of reference light beams having different phases in a plane perpendicular to a direction in which the light emitted from the light source travels, a CCD camera having an image-capturing plane on which two kinds of interference fringe patterns are recorded, the interference fringe patterns being formed by interferences between the two kinds of reference light beams, and the object light beams, and an image reconstruction device that generates a reconstructed image of the subject from the two kinds of interference fringe patterns recorded on the image-capturing plane.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 4, 2014
    Assignee: National University Corporation Kyoto Institute of Technology
    Inventors: Yasuhiro Awatsuji, Atsushi Kaneko, Takamasa Koyama, Tatsuki Tahara, Takeshi Wakamatsu
  • Patent number: 8665502
    Abstract: An image reading device includes a transporter transporting a document to a reading position, a first corrector correcting a skew of the document by coming into contact with a leading edge thereof, a radiating unit radiating light to the document, an image-information acquiring unit acquiring image information of the document based on information of light reflected therefrom, a reflector reflecting the radiated light, a leading-edge detector comparing a quantity of light reflected by the reflector with a quantity of light reflected by the document so as to detect the leading edge, a skew-amount calculator calculating a skew amount of the leading edge, and a second corrector correcting a skew of the image information based on the skew amount. The device switches between the skew correction by the first corrector and the skew correction by the second corrector based on document information, the skew amount, or user's selection.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 4, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shinji Masaki, Atsushi Kaneko, Hiromi Kita, Kenji Yamada, Nobutoshi Hamasaki, Nobuyuki Maruno
  • Publication number: 20140040460
    Abstract: An information processing apparatus executes a process and a second server in an information processing system including a first server, the second server, and a third server. The process includes: collecting, in a first queue, traffic data that is transmitted and received by the second server; acquiring, from the first server, a client request reception time when the first server receives a request from a client and a client response time when the first server responds to the request from the client; and moving, to a second queue, traffic data of a time period from a first server request reception time when the second server receives a request from the first server after the client request reception time to a first server response time when the second server responds to the request from the first server before the client response time.
    Type: Application
    Filed: June 12, 2013
    Publication date: February 6, 2014
    Inventors: Akihiko SAKURAI, Eiji Mizunuma, Atsushi Kaneko, Hideki Gou, Kazutaka Taniguchi, Takashi Yamashita, Takahiko Shirazawa
  • Publication number: 20130344474
    Abstract: The novel means by which whether a subject has chronic hepatitis B or not can be determined easily with a high degree of accuracy is disclosed. The method for detection of chronic hepatitis B according to the present invention comprises measuring the amount of anti-HBc IgG in a sample separated from a subject. In this method, the measured amount of anti-HBc IgG which is not less than a predetermined cut-off value is indicative of chronic hepatitis B in the subject. The cut-off value may be a value not less than 40 IU/mL, e.g., a value selected from the range of 100 IU/mL to 200 IU/mL. By the present invention, chronic hepatitis B can be detected based on the amount of anti-HBc IgG without measuring the total amount of HBc antibodies including anti-HBc IgM.
    Type: Application
    Filed: December 21, 2012
    Publication date: December 26, 2013
    Applicants: NATIONAL HOSPITAL ORGANIZATION, FUJIREBIO INC.
    Inventors: Hiroshi YATSUHASHI, Atsushi KANEKO, Chiaki TAKAHASHI
  • Patent number: 8615732
    Abstract: Methods and articles of manufacture for integrated, automatic pseudo localization of software applications are disclosed herein. A pseudo localization process, comprised of one or more utility applications, is integrated into a build cycle for a developing software application to generate pseudo-translated user-interface code as part of a build process. A build application may then generate a pseudo-language build of the developing software application and/or development database to enable testing and identification of internationalization defects that would prevent effective localization of the software product for the international market.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: December 24, 2013
    Assignee: Siebel Systems, Inc.
    Inventors: Atsushi Kaneko, Hans E. E. Kedefors
  • Patent number: 8592896
    Abstract: A semiconductor device includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode housed in the trench with a gate insulator intervening, a top surface of the gate electrode being lower than a top surface of the second diffused region, a first oxide film housed in the trench and formed over the gate electrode, a second oxide film housed in the trench and formed over the first oxide film, a third oxide film housed in the trench and formed over the second oxide film, and a source electrode formed over the third oxide film and electrically connecting to the first and second diffused regions.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Atsushi Kaneko, Hideo Yamamoto
  • Patent number: 8585060
    Abstract: A mechanical seal device for obtaining appropriate sliding properties under any conditions, such as a pressure of seal is low or high. Both first grooves 463 and second grooves 464 are formed on a sliding face 46 of a stationary ring 46. The first grooves which are not in communication externally and act for reducing contact resistance of a sliding face by a dynamic pressure action when a rotary shaft rotates, the second grooves act for reducing the contact resistance of the sliding face constantly by introducing a pressure from external. Thus, a mechanical seal device which is available to seal sealed fluid under an appropriate dry contact status wherein a sliding face load is reduced in any condition can be provided.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: November 19, 2013
    Assignee: Eagle Industry Co., Ltd.
    Inventors: Yoji Oshii, Koji Akiyama, Joji Watanabe, Atsushi Kaneko
  • Patent number: 8570766
    Abstract: A shield case includes a first shield member and a second shield member coupled to the first shield member to form the shield case. A concave portion is capable of accommodating a sealing member for sealing inner space of the shield case by contacting the first shield member and the second shield member, and is formed on the second shield member. On each of the first shield member and the second shield member, a paint film portion is formed on an area of the shield case external to the concave portion. On the first shield member or the second shield member or combination thereof, a convex portion is formed on the area of the shield case on the inner space side and internal to the concave portion. The surfaces of the first shield member and the second shield member contact each other at the convex portion.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: October 29, 2013
    Assignee: Fujitsu Limited
    Inventors: Kazuya Noguchi, Hiromi Maeda, Toshimitsu Kobayashi, Atsushi Kaneko, Yoshihiro Waki, Masaki Yamamoto
  • Publication number: 20130260401
    Abstract: The invention intends to provide a bioassay method using a simple in-vitro test for Daikinchuto, and further to provide a more highly accurate method for quality control of Daikenchuto using the same. These methods are a bioassay method for the pharmacological activity of Daikenchuto, characterized in that a test sample containing Daikenchuto is added to cultured serotonin-producing cells, and the serotonin content in the culture supernatant is subsequently measured; and a quality control method for Daikenchuto preparations in which the pharmacological activity of a test preparation and a reference preparation for which the pharmacological effect as Daikenchuto has been clinically confirmed are evaluated under the same conditions, and the equivalence of the reference preparation and testing preparation is evaluated.
    Type: Application
    Filed: November 28, 2011
    Publication date: October 3, 2013
    Applicant: Tsumura & Co.
    Inventors: Atsushi Kaneko, Nagisa Ohno
  • Publication number: 20130182296
    Abstract: An image reading device includes a transporter transporting a document to a reading position, a first corrector correcting a skew of the document by coming into contact with a leading edge thereof, a radiating unit radiating light to the document, an image-information acquiring unit acquiring image information of the document based on information of light reflected therefrom, a reflector reflecting the radiated light, a leading-edge detector comparing a quantity of light reflected by the reflector with a quantity of light reflected by the document so as to detect the leading edge, a skew-amount calculator calculating a skew amount of the leading edge, and a second corrector correcting a skew of the image information based on the skew amount. The device switches between the skew correction by the first corrector and the skew correction by the second corrector based on document information, the skew amount, or user's selection.
    Type: Application
    Filed: July 11, 2012
    Publication date: July 18, 2013
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Shinji MASAKI, Atsushi KANEKO, Hiromi KITA, Kenji YAMADA, Nobutoshi HAMASAKI, Nobuyuki MARUNO
  • Patent number: 8476199
    Abstract: This invention provides a rare earth-type tape-shaped oxide superconductor having excellent mechanical strength and superconducting properties and a composite substrate using for the same. Non-oriented and non-magnetic Ni-9 at % W alloy tapes (11, 21) were bonded onto both sides of a non-oriented and non-magnetic hastelloy tape (100) by a normal temperature bonding process, and an Ni-3 at % W alloy tape (12) having a cubic texture was bonded onto the surface of the tape (11) by a normal temperature bonding process. Thereafter, the heat-treatment was given in a reducing atmosphere and a bonding layer (50a) etc. was formed on the adhesive interface of each layer. Next, a (Ce, Gd)O2 intermediate layer (13) and a Ce2Zr2O7 intermediate layer (14) by an MOD process, a CeO2 intermediate layer (15), a YBCO superconducting film (16) by a TFA-MOD method, and a silver stabilization layer (17) were stacked sequentially on the surface of the tape (12). A critical current value (Ic) of this superconductor showed 150 A.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: July 2, 2013
    Assignees: International Superconductivity Technology Center, The Juridicial Foundation, SWCC Showa Cable Systems Co., Ltd.
    Inventors: Yuji Aoki, Tsutomu Koizumi, Yasuo Takahashi, Atsushi Kaneko, Takayo Hasegawa, Hiroshi Nakamura
  • Publication number: 20130142540
    Abstract: A cleaning device includes first to third cleaning members that clean a surface of an endless belt that is looped over rollers including a driving roller. The first cleaning member is brought into contact with and separated from the surface at a predetermined timing. The second cleaning member is disposed upstream of the first cleaning member and downstream of the driving roller in a movement direction of the endless belt. The second cleaning member is in contact with the endless belt so as to prevent a tension variation of the endless belt caused by the first cleaning member from affecting the driving roller. The third cleaning member is disposed downstream of the first cleaning member. A contact state in which the third cleaning member is in contact with the endless belt is switched from a first contact state to a second contact state so as to reduce the tension variation.
    Type: Application
    Filed: May 31, 2012
    Publication date: June 6, 2013
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Atsushi KANEKO, Kazuyoshi HAGIWARA, Masaaki TOKUNAGA, Kazutoshi SUGITANI, Koichi SATO, Tsutomu KOMIYAMA
  • Patent number: 8431515
    Abstract: A tape-shaped oxide superconductor includes a 15 to 100 nm-thick Ce—Gd—O-based oxide layer (Ce:Gd=40:60 to 70:30 molar ratio) and a 100 nm-thick Ce—Zr—O-based oxide layer (Ce:Zr=50:50 molar ratio) as first and second intermediate layers are formed by MOD on an Ni-base alloy substrate having a half value width (FWHM:??) of 6.5 degrees. A 150 nm-thick CeO2 oxide layer as a third intermediate layer is formed on the second intermediate layer by RF sputtering. A 1 ?m-thick YBCO superconducting layer is formed by TFA-MOD on the three-layer structure. In the tape-shaped oxide superconductor, the ?? values of the first to third intermediate layers are (6.0 to 6.5) degrees, (6.0 to 6.6) degrees, and (6.0 to 6.6) degrees, respectively, and the Jc value of the YBCO superconducting layer in liquid nitrogen is 1.8 to 2.2 MA/cm2.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: April 30, 2013
    Assignees: International Superconductivity Technology Center, The Juridical Foundation, SWCC Showa Cable Systems Co., Ltd.
    Inventors: Yasuo Takahashi, Tsutomu Koizumi, Yuji Aoki, Atsushi Kaneko, Takayo Hasegawa
  • Patent number: 8415740
    Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: April 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Atsushi Kaneko
  • Publication number: 20130085071
    Abstract: Disclosed are an oxide superconductor tape and a method of manufacturing the oxide superconductor tape capable of improving the length and characteristics of superconductor tape and obtaining stabilized characteristics across the entire length thereof. A Y-class superconductor tape (10), as an oxide superconductor tape, comprises a tape (13) further comprising a tape-shaped non-oriented metallic substrate (11), and a first buffer layer (sheet layer) (12) that is formed by IBAD upon the tape-shaped non-oriented metallic substrate (11); and a second buffer layer (gap layer) (14), further comprising a lateral face portion (14a) that is extended to the lateral faces of the first buffer layer (sheet layer) (12) upon the tape (13) by RTR RF-magnetron sputtering.
    Type: Application
    Filed: February 10, 2011
    Publication date: April 4, 2013
    Inventors: Tatsuhisa Nakanishi, Yuji Aoki, Tsutomu Koizumi, Atsushi Kaneko, Takayo Hasegawa
  • Patent number: 8310005
    Abstract: A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Publication number: 20120126316
    Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.
    Type: Application
    Filed: January 26, 2012
    Publication date: May 24, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Atsushi KANEKO