Patents by Inventor Atsushi Kaneko

Atsushi Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100258863
    Abstract: A semiconductor device according to the present invention having a vertical MOSFET that includes a first trench that is formed in a semiconductor substrate and includes a gate electrode of the vertical MOSFET embedded therein with a gate insulating film interposed therebetween, a second trench that is connected with the first trench and has a trench width wider than the first trench, a gate pad that is connected with the gate electrode and formed to a sidewall of the second trench with the gate insulating film interposed therebetween, and a gate line that is connected with a sidewall of the gate pad and electrically connects with the gate electrode via the gate pad.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 14, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: ATSUSHI KANEKO
  • Publication number: 20100253986
    Abstract: Provided is a digital holography device having a simple configuration and an improved image quality, including: a light source that emits light, the light source being provided for supply of object light beams formed by radiation, transmission, scattering, reflection, or diffraction of the emitted light from a subject; an array device that splits the light emitted from the light source into two kinds of reference light beams having different phases in a plane perpendicular to a direction in which the light emitted from the light source travels; a CCD camera having an image-capturing plane on which two kinds of interference fringe patterns are recorded, the interference fringe patterns being formed by interferences between the two kinds of reference light beams, which have been produced by the array device, and the object light beams, which have been formed by radiation, transmission, scattering, reflection, or diffraction from the subject; and an image reconstruction device that generates a reconstructed imag
    Type: Application
    Filed: November 21, 2008
    Publication date: October 7, 2010
    Inventors: Yasuhiro Awatsuji, Atsushi Kaneko, Takamasa Koyama, Tatsuki Tahara, Takeshi Wakamatsu
  • Patent number: 7776693
    Abstract: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: August 17, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko, Yoshimitsu Murase
  • Publication number: 20100197506
    Abstract: This invention provides a tape-shaped oxide superconductor which can prevent the diffusion of elements constituting a metallic substrate into a superconducting layer and cracking of an intermediate layer and improve the orientation of the superconducting layer. A 15 to 100 nm-thick Ce—Gd—O-based oxide layer (2) (Ce:Gd=40:60 to 70:30 molar ratio) as a first intermediate layer and a 100 nm-thick Ce—Zr—O-based oxide layer (3) (Ce:Zr=50:50 molar ratio) as a second intermediate layer are formed by an MOD method on an Ni-base alloy substrate (1) having a half value width (FMHW: ??) of 6.5 degrees. A 150 nm-thick CeO2 oxide layer (4) as a third intermediate layer is further formed on the second intermediate layer by an RF sputtering method. A 1 ?m-thick YBCO superconducting layer (5) is formed by a TFA-MOD method on the intermediate layer having a three-layer structure. In the tape-shaped oxide superconductor, the ?? values of the first to third intermediate layers are (6.0 to 6.5) degrees, (6.0 to 6.
    Type: Application
    Filed: May 7, 2008
    Publication date: August 5, 2010
    Applicants: SWCC SHOWA CABLE SYSTEMS CO., LTD, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION
    Inventors: Yasuo Takahashi, Tsutomu Koizumi, Yuji Aoki, Atsushi Kaneko, Takayo Hasegawa
  • Patent number: 7761288
    Abstract: Systems and methods for software development in which the development of a base product proceeds concurrently with the internationalization and localization of the base product to produce multiple language versions of the product for polylingual simultaneous shipment to customers wherein one or more of the multiple languages can be uploaded by the customer in a single installation process.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: July 20, 2010
    Assignee: Siebel Systems, Inc.
    Inventors: Karen P. Parnell, Hans Eric Emanuel Kedefors, Atsushi Kaneko, Daniel Salzer, Jayant Kulkarni, Mark Curtis Hastings, Nikolai Tsepalov, David A Murphy, Giona Lorenzo Jorge
  • Publication number: 20100171172
    Abstract: A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 8, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Publication number: 20100123191
    Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.
    Type: Application
    Filed: November 19, 2009
    Publication date: May 20, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: ATSUSHI KANEKO
  • Patent number: 7704827
    Abstract: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n? epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Publication number: 20100099573
    Abstract: This invention provides a rare earth-type tape-shaped oxide superconductor having excellent mechanical strength and superconducting properties and a composite substrate using for the same. Non-oriented and non-magnetic Ni-9 at % W alloy tapes (11, 21) were bonded onto both sides of a non-oriented and non-magnetic hastelloy tape (100) by a normal temperature bonding process, and an Ni-3 at % W alloy tape (12) having a cubic texture was bonded onto the surface of the tape (11) by a normal temperature bonding process. Thereafter, the heat-treatment was given in a reducing atmosphere and a bonding layer (50a) etc. was formed on the adhesive interface of each layer. Next, a (Ce, Gd) O2 intermediate layer (13) and a Ce2Zr2O7 intermediate layer (14) by an MOD process, a CeO2 intermediate layer (15), a YBCO superconducting film (16) by a TFA-MOD method, and a silver stabilization layer (17) were stacked sequentially on the surface of the tape (12). A critical current value (Ic) of this superconductor showed 150 A.
    Type: Application
    Filed: February 21, 2008
    Publication date: April 22, 2010
    Inventors: Yuji Aoki, Tsutomu Koizumi, Yasuo Takahashi, Atsushi Kaneko, Takayo Hasegawa, Hiroshi Nakamura
  • Publication number: 20100090919
    Abstract: A plate-shaped radiating element of a shape having at least three planes is formed by bending a metal plate having a substantially rectangular shape. A first slit is provided from a lower edge of the plate-shaped radiating element up to a portion in the vicinity of an upper edge of the plate-shaped radiating element while passing through a center point of the plate-shaped radiating element, and forms plate-shaped dipole elements on both sides thereof. A second slit is provided parallel to the upper edge of the plate-shaped radiating element and forms a folded element on an upper side thereof. Feeding points are provided on both sides of the first slit at the lower edge of the plate-shaped radiating element.
    Type: Application
    Filed: December 14, 2009
    Publication date: April 15, 2010
    Applicant: YAGI ANTENNA INC.
    Inventors: ATSUSHI KANEKO, Shuji Hagiwara
  • Patent number: 7652327
    Abstract: To provide a semiconductor device capable of reducing a gate capacitance, and preventing breakdown of a gate oxide film if a large amount of current flows. A semiconductor device according to an embodiment of the present invention includes: an epitaxial layer; a channel region formed on the epitaxial layer; a trench extending from a surface of the channel region to the epitaxial layer; a gate oxide film that covers an inner surface of the trench; a gate electrode filled into the trench; and a buried insulating film formed below the gate electrode and away from the gate oxide film.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: January 26, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Kaneko
  • Patent number: 7648415
    Abstract: A game apparatus includes a game machine and a game cartridge. On a case of the game machine, operation buttons are provided. On the LCD, game images of a player object and non-player objects in a game space are displayed. For example, a player, by holding the case with both hands and operating the operation buttons, controls a holding action of a left hand and a right hand of the player object. When the player instructs the player object to perform the holding action, if the non-player object exists at a position where the hand of the player object exists, the non-player object is held. In a case that the player object holds the non-player object with one hand, the player object rotates, and by changing the non-player object to be held, the player object can move within the game space. Furthermore, if releasing the hand from it during the rotation, the player object jumps out.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: January 19, 2010
    Assignee: Nintendo Co., Ltd.
    Inventors: Toshiharu Izuno, Atsushi Kaneko, Masataka Sato
  • Publication number: 20100007014
    Abstract: According to an aspect of the invention, a semiconductor device includes: a semiconductor substrate; a memory chip disposed on the semiconductor substrate, the memory chip including: a first face that is not opposed to the semiconductor substrate; and a plurality of first pads disposed on the first face so that the first pads are aligned along a virtual line passing at a central portion on the first face; a controller chip disposed on the first face not to cover the first pads, the controller chip including: a second face that is not opposed to the first face; and a plurality of second pads disposed on the second face so that the second pads are aligned along at least one side of the second face; and a plurality of metal wires electrically connecting the first pads and the second pads.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 14, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hidetoshi Suzuki, Isao Ozawa, Atsushi Kaneko, Yuka Matsunaga
  • Publication number: 20090121957
    Abstract: A plate-shaped radiating element of a shape having at least three planes is formed by bending a metal plate having a substantially rectangular shape. A first slit is provided from a lower edge of the plate-shaped radiating element up to a portion in the vicinity of an upper edge of the plate-shaped radiating element while passing through a center point of the plate-shaped radiating element, and forms plate-shaped dipole elements on both sides thereof. A second slit is provided parallel to the upper edge of the plate-shaped radiating element and forms a folded element on an upper side thereof. Feeding points are provided on both sides of the first slit at the lower edge of the plate-shaped radiating element.
    Type: Application
    Filed: March 15, 2006
    Publication date: May 14, 2009
    Applicant: YAGI ANTENNA INC.
    Inventors: Atsushi Kaneko, Shuji Hagiwara
  • Publication number: 20090072300
    Abstract: The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET 100 comprises a plurality of gate trenches 7 which is arranged in stripes, an array which is sandwiched with the plurality of gate trenches 7 and includes N+ source regions 4N+ and P+ base contact regions 5P+, and a diode region (anode region 6P+) which is formed so as to contact with two gate trenches 7. The N+ source regions 4N+ and the base contact regions 5P+ are alternately arranged along a longitudinal direction of the gate trench 7. Size of the diode region (anode region 6P+) corresponds to at least one of the N+ source regions 4N+ and two of the P+ base contact regions 5P+.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 19, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Hideo Yamamoto, Kenya Kobayashi, Atsushi Kaneko
  • Publication number: 20090057723
    Abstract: A semiconductor device including a plurality of semiconductor elements, a substrate on which the plurality of semiconductor elements are mounted, the substrate also having a plurality of terminals for connecting to external equipment, a fuse mounted on the outside of a mounting area of the plurality of semiconductor elements and mounted on a surface of the substrate near a power supply terminal among the plurality of terminals, and the power supply terminal and the plurality of semiconductor elements are connected via the fuse.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Kaneko, Yasuo Okada
  • Patent number: 7488163
    Abstract: A trochoid oil pump, which enables the endurance to be increased and the reduction of discharge pulsations and noise to be achieved, and in which those results can be realized with a very simple structure. An interdental space constituted by an inner rotor and an outer rotor having trochoid tooth profile or substantially trochoid tooth profile starts a compression stroke in the location of a partition section between an intake port and a discharge portion, and a linking gap L is composed by the interdental space and a preceding adjacent interdental space realized in a discharge stroke. The linking gap expands gradually from the start of compression stroke to the discharge stroke.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: February 10, 2009
    Assignee: Yamada Manufacturing Co., Ltd.
    Inventors: Kazuo Enzaka, Masahiro Kasahara, Yasunori Ono, Kenichi Fujiki, Keiichi Kai, Yoshiaki Senga, Atsushi Kaneko
  • Patent number: 7435066
    Abstract: The present invention provides an oil pump in which eroding of the inside of the pump due to cavitation and erosion is prevented by minimizing the pressure change in a fluid when inter-tooth spaces formed by an inner rotor and an outer rotor transport the fluid from the intake port to the discharge port. The oil pump comprises: an inner rotor; an outer rotor; an intake port; a discharge port; a transfer side partition part formed between a terminal end of the intake port and a leading end of the discharge port; and a shallow groove which is formed in the transfer side partition part, and which communicates with the discharge port but does not communicate with the intake port. The shallow groove does not intersect with the cell on the transfer side partition part, and is positioned farther inward than the circular locus of the gear bottom parts of the inner rotor.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: October 14, 2008
    Assignee: Yamada Manufacturing Co., Ltd.
    Inventors: Kazuo Enzaka, Yasunori Ono, Sentaro Nishioka, Masahiro Kasahara, Atsushi Kaneko
  • Publication number: 20080142799
    Abstract: Disclosed herewith is a semiconductor device comprising a trench gate electrode and a zener diode, as well as a method for manufacturing the same. The trench gate electrode is formed in a semiconductor body and includes a first polycrystalline silicon layer doped with impurities of a first conductivity type at a first concentration. An extended gate electrode is elongated over the semiconductor body in contact with the trench gate electrode, and includes a second polycrystalline silicon layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration. The zener diode is formed over the semiconductor body and includes a third polycrystalline silicon layer of a first conductivity type and a fourth polycrystalline silicon layer of a second conductivity type.
    Type: Application
    Filed: November 21, 2007
    Publication date: June 19, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Atsushi Kaneko
  • Publication number: 20080135921
    Abstract: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n? epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
    Type: Application
    Filed: November 13, 2007
    Publication date: June 12, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko