Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, word lines connected to the memory cell array to select rows of the memory cell array, first bit lines connected to the memory cell array to select columns of the memory cell array, a replica cell array including replica cells respectively connected to the word lines, and storing information on characteristics of the rows of the memory cell array, and a second bit line connected to the replica cells. An operation is changed for each row of the memory cell array based on the information in the replica cells.

Abstract: According to an embodiment, a semiconductor memory includes word lines, a plurality of sets of a pair of bit lines, memory cells, a writing/reading circuit, and a word line selection circuit. In a state where inverted data of program data has been written to the memory cells, a stress is applied and the program data is programmed to the memory cells. The writing/reading circuit writes the inverted data of the same program data to a unit memory cell group made of memory cells connected to a set of a pair of bit lines at a time of programming, and reads data from the unit memory cell group by detecting a signal level of the pair of bit lines at a time of reading. The word line selection circuit simultaneously selects and drives two or more word lines of the word lines connected to the unit memory cell group.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the memory cells; a global bit line to be commonly connected to a plurality of the local bit lines; and switch circuits connected between the local bit lines and the global bit line. The switch circuits connect the global bit line to one of the local bit lines, the one of the local bit lines being electrically connected to the memory cells of the group located at a position specified by select information of the first direction and the second direction.

Abstract: A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.

Abstract: According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

Abstract: A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first and second bit lines. The sense amplifier includes a first and a second drive transistor configuring a transistor pair for differential amplification, and a first and a second capacitor connected between the sources of the first and second drive transistors and a source control terminal, respectively. The sense amplifier precharges the first and second drive transistors on the drain side prior to sensing, thereby holding the threshold information on the first and second drive transistors in the first and second capacitors, and compensates for the source voltages on the first and second drive transistors by the threshold information held in the first and second capacitors at the time of sensing.

Abstract: According to one embodiment, a magnetoresistive memory device includes first and second bit lines, a memory cell, a power supply line, first and second transistors, and third and fourth transistors. The memory cell has first and second magnetoresistive elements and is connected between the first and second bit lines. The power supply line is connected between the first and second magnetoresistive elements. The first and second transistors have current paths inserted in the first and second bit lines, respectively, and have gate electrodes connected, respectively to the second and first bit lines provided on a side opposite to the memory cell. The third and fourth transistors are inserted in the first and second bit lines. Gate electrodes of the third and fourth transistors are cross-coupled, and the third and fourth transistors are controlled by current from the memory cell.

Abstract: According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided in intersection portions of the plurality of word lines and the plurality of bit lines. The plurality of sense amplifiers is configured to detect a signal level of the corresponding bit lines. The timing generation circuit includes a timing selection circuit configured to select a timing in a preset order from among timings in which each bit line signal in the plurality of bit lines changes. The timing generation circuit is configured to generate activation timing to activate the plurality of sense amplifiers based on the selected timing.

Abstract: The battery pack is provided with an analog front-end that detects battery voltage, and a micro-controller connected to the analog front-end that accepts analog voltage signals from the analog front-end as input. The micro-controller switches voltage signals input from the analog front-end to determine failure of the analog front-end or the micro-controller.

Abstract: According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, word lines connected to the memory cell array to select rows of the memory cell array, first bit lines connected to the memory cell array to select columns of the memory cell array, a replica cell array including replica cells respectively connected to the word lines, and storing information on characteristics of the rows of the memory cell array, and a second bit line connected to the replica cells. An operation is changed for each row of the memory cell array based on the information in the replica cells.

Abstract: A remaining capacity calculating section is provided that acquires a discharged capacity of a rechargeable battery based on a discharging current and a discharging time of the rechargeable battery, and calculates a relative remaining capacity of the rechargeable battery based on the discharged capacity and the fully-charged capacity of the rechargeable battery. The remaining capacity calculating section employs the rating capacity of the rechargeable battery or a learned fully-charged capacity as the fully-charged capacity when a high capacity mode is selected, and employs a capacity obtained by multiplying the rating capacity or learned fully-charged capacity by a predetermined factor not more than 1 as the fully-charged capacity when a long life mode is selected.

Abstract: According to one embodiment, a memory cell stores therein data. In a bit line, a potential changes according to write data to be written in the memory cell. A precharge circuit precharges the bit line. A precharge control circuit controls precharge of the bit line based on the potential of the bit line and the write data.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the memory cells; a global bit line to be commonly connected to a plurality of the local bit lines; and switch circuits connected between the local bit lines and the global bit line. The switch circuits connect the global bit line to one of the local bit lines, the one of the local bit lines being electrically connected to the memory cells of the group located at a position specified by select information of the first direction and the second direction.

Abstract: A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first and second bit lines. The sense amplifier includes a first and a second drive transistor configuring a transistor pair for differential amplification, and a first and a second capacitor connected between the sources of the first and second drive transistors and a source control terminal, respectively. The sense amplifier precharges the first and second drive transistors on the drain side prior to sensing, thereby holding the threshold information on the first and second drive transistors in the first and second capacitors, and compensates for the source voltages on the first and second drive transistors by the threshold information held in the first and second capacitors at the time of sensing.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node, and a control circuit which changes the amount of current of the pair of bit lines in accordance with the amplitude of the pair of bit lines for each column in a memory macro, that is formed by arranging the plurality of memory cells in a matrix, in the data read operation of each of the plurality of memory cells.

Abstract: The battery pack is provided with an analog front-end that detects battery voltage, and a micro-controller connected to the analog front-end that accepts analog voltage signals from the analog front-end as input. The micro-controller switches voltage signals input from the analog front-end to determine failure of the analog front-end or the micro-controller.

Abstract: A battery pack updating method updates firmware stored in internal control circuit memory via an update signal sent from a main device that supplies power. When battery pack memory is updated, an AC adapter is connected to the main device, and power is supplied to the main device from the AC adapter. The updating method transmits a charging and discharging blocking signal from the main device to the battery pack control circuit via a communication line. The charging and discharging blocking signal stops discharge from the battery pack rechargeable battery, and stops charging of the rechargeable battery. With rechargeable battery discharging and charging to and from the main device stopped by the charging and discharging blocking signal, the updating method transmits update data from the main device to the battery pack control circuit to update memory.

Abstract: A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.

Abstract: A MOSFET 61 is connected between a power supply IC6 and a 3.3-V power supply terminal. When the MOSFET 61 is turned OFF, a control circuit board 100 is shut down which includes a control portion 5 for calculating RSOC (remaining capacity ratio). When the control circuit board 100 returns from shutdown, the maximum cell voltage is detected as OCV (open circuit voltage). RSOC can be calculated based on the maximum cell voltage by using the discharge characteristic which relates OCV to RSOC. In this case, a quadratic curve line segment is selected from an approximate curve line which approximates the discharge characteristics. RSOC can be calculated by substituting the detected maximum cell voltage into the quadratic function which is represented by the selected quadratic curve line segment.