Abstract: SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor.

Abstract: A battery pack includes a switching element, a heat resistor, and a fuse. The switching element turns to ON if the battery pack becomes in an abnormal state. The heat resistor is connected to the switching element and a battery in series. Current flows through the heat resistor when the switching element turns to ON. The fuse is located in a position where the fuse is heated by the heat resistor through which the current flows. The fuse is connected to the battery in series so that the fuse is disconnected with heat by the heat resistor at high temperature. Thus, the fuse cuts off a current flow in the battery. If the battery pack is in an abnormal state, when the capacity or voltage of the battery is less than a preset capacity or voltage value, the fuse is disconnected with heat by turning the switching element to ON.

Abstract: A semiconductor integrated circuit device includes a first semiconductor circuit, a second semiconductor circuit, a first control circuit and a second control circuit. The first and second semiconductor circuits are formed on a semiconductor substrate and operate using a voltage provided by an external power supply circuit as a power supply voltage. The first control circuit is formed on the semiconductor substrate and holds control information used to control the voltage generated by the external power supply circuit in accordance with operating performance of the first and second semiconductor circuits. The second control circuit controls a property of the first semiconductor circuit in accordance with the control information held by the first control circuit.

Abstract: A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.

Abstract: The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors. When offset information of the memory cell is to be read, a voltage applied to the first power supply terminal and a voltage applied to the second power supply terminal are made equal. Then the voltage applied to the first power supply terminal is returned to the first potential, and the voltage applied to the second power supply terminal is returned to the second potential. When stress is generated in the first to fourth transistor included in the first or second inverter, the potential difference between the first power supply terminal and the second power supply terminal is made larger than a difference between the first potential and the second potential.

Abstract: A battery pack provided with a current cut-off device connected in series with batteries, a tamper detector to detect tampering and issue a tamper signal, and a control circuit connected to the tamper detector. If the tamper detector detects tampering with the battery pack, the control circuit switches the current cut-off device off to shut off current to the batteries, or it issues a tamper signal.

Abstract: The battery pack is provided with an analog front-end 2 that detects battery 1 voltage, and a micro-controller 3 connected to the analog front-end 2 that accepts analog voltage signals from the analog front-end 2 as input. The micro-controller 3 switches voltage signals input from the analog front-end 2 to determine failure of the analog front-end 2 or the micro-controller 3.

Abstract: Systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are performed immediately following the write operation and are directed to the same data. In one embodiment, a memory system includes an array of a first type of memory cells and a register having cells of a second type. The second type of cells is designed to stabilize data more quickly than the first type. Data is written concurrently into the memory array and the register. When a read operation is directed to the location of an immediately preceding write operation, the data is read from the register. When a read operation is directed to a location that is not coincident with an immediately preceding write operation, the data is read from the memory array.

Abstract: A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines,

Abstract: A charging method includes first and second charging steps to charge a lithium-ion battery. In the first charging step, a temperature rise gradient of the battery to a current is detected. A battery temperature when the battery is charged to a first predetermined capacity is predicted based on the gradient. A charging current is controlled based on the predicted temperature. The battery is charged, at a current that brings a battery temperature lower than a predetermined temperature, to the first predetermined capacity. In the second charging step, a temperature rise gradient of the battery is detected. A battery temperature when the battery is charged to a second predetermined capacity is predicted based on the gradient. A charging current is controlled based on the predicted temperature. The battery is charged, at a current that brings the temperature of the battery lower than the predetermined temperature, to the second predetermined capacity.

Abstract: A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potential of any one of the pair of bit lines. A write circuit is arranged, separately from the read circuit, at the other side of the memory cell array. The write circuit provides written data to the pair of bit lines to write data to the SRAM cells.

Abstract: According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor, a first N-channel MOS transistor, a second inverter being composed of a second p-channel MOS transistor and a second N-channel transistor, a data-retaining portion having a third N-channel MOS transistor, a fourth N-channel MOS transistor, a fifth N-channel MOS transistor and a sixth N-channel MOS transistor, a data-reading portion for reading out data stored in the data-retaining portion via a first bit line, including at least one N-channel MOS transistor, wherein gate widths of the fifth N-channel MOS transistor and the sixth N-channel MOS transistor, respectively, is larger than gate widths of the first N-channel MOS transistor, the second N-channel MOS transistor, the third N-channel MOS transistor, the fourth N-channel MOS transistor, the first P-channel MOS transistor and the second P-channel MOS transistor, respectively.

Abstract: SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor.

Abstract: This disclosure concerns a LSI comprising two bit lines; two input nodes; sense nodes transmitting a signal difference input to the two input nodes; an output node outputting the amplified signal; a current adjustment gate adjusting an amount of current flowing through one of the two sense nodes; a latch circuit controlling the current adjustment gate; two signal lines transmitting a voltage source and a comparison voltage via the two input nodes, the comparison voltage being obtained by subtracting a predetermined threshold voltage from the power source voltage; and two switching elements provided between the two input nodes and the two signal lines, wherein the latch circuit switches the current adjustment gate in the case where the amplified signal is an inversion signal of an amplified signal according to the threshold voltage when the power source voltage and the comparison voltage are respectively applied to the two input nodes.

Abstract: Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a transfer device controlled by a pre-read signal. In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable. By shifting the bitline voltage before the wordline is turned on, the accessed cell is relieved from the stress which would have otherwise caused cell stability problems.

Abstract: Systems and methods for a memory system capable of detection and repair of failures occurring during operation are disclosed. Embodiments of the present invention provide a memory system operable to detect an error at a memory cell of a memory and replace the failed memory cell. More specifically, in certain embodiments, a failure at a certain address of a memory may be detected during operation of the memory. This memory cell may then be replaced by a redundant memory cell. By replacing the failed memory cell the memory system may continue to be utilized without encountering subsequent errors due to the failed memory cell.

Abstract: A first transfer transistor includes a first diffusion layer connected to a first bit line, and a second diffusion layer connected to a first storage node, the first diffusion layer is provided in a substrate, the second diffusion layer is provided in a bottom part of a recess provided in the substrate, a channel region of the first transfer transistor is offset with respect to the second diffusion layer toward the first storage node, and the offset part functions as a resistor.

Abstract: A semiconductor integrated circuit device includes a first semiconductor circuit, a second semiconductor circuit, a first control circuit and a second control circuit. The first and second semiconductor circuits are formed on a semiconductor substrate and operate using a voltage provided by an external power supply circuit as a power supply voltage. The first control circuit is formed on the semiconductor substrate and holds control information used to control the voltage generated by the external power supply circuit in accordance with operating performance of the first and second semiconductor circuits. The second control circuit controls a property of the first semiconductor circuit in accordance with the control information held by the first control circuit.

Abstract: Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a transfer device controlled by a pre-read signal. In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable. By shifting the bitline voltage before the wordline is turned on, the accessed cell is relieved from the stress which would have otherwise caused cell stability problems.

Abstract: This disclosure concerns a LSI comprising two bit lines; two input nodes; sense nodes transmitting a signal difference input to the two input nodes; an output node outputting the amplified signal; a current adjustment gate adjusting an amount of current flowing through one of the two sense nodes; a latch circuit controlling the current adjustment gate; two signal lines transmitting a voltage source and a comparison voltage via the two input nodes, the comparison voltage being obtained by subtracting a predetermined threshold voltage from the power source voltage; and two switching elements provided between the two input nodes and the two signal lines, wherein the latch circuit switches the current adjustment gate in the case where the amplified signal is an inversion signal of an amplified signal according to the threshold voltage when the power source voltage and the comparison voltage are respectively applied to the two input nodes.