Abstract: A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and retrieving, by an assist circuit trimming (ACT) circuit, the address information of the first bit from the memory device to selectively activate at least a first one of a plurality of assist circuits associated with the first bit.

Abstract: A method of controlling a wordline by a driver decoder circuit includes generating a first control signal having a first logically high level and a first logically low level, and generating a second control signal having a second logically high level when the first control signal has the first logically high level and a second logically low level when the first control signal has the first logically low level. The first logically high level is different from the second logically high level, and the first logically low level is different from the second logically low level. The method includes coupling the wordline to a first node having a first voltage value in response to the first control signal having the first logically low level and decoupling the wordline from a second node having a second voltage value in response to the second control signal having the second logically low level.

Abstract: A memory macro includes a plurality of columns and a plurality of switching circuits. A column of the plurality of columns has a plurality of voltage supply nodes corresponding to a plurality of memory cells in the column. A switching circuit of the plurality of switching circuits corresponds to a column of the plurality of columns and is configured to selectively provide a first voltage value of a first voltage source or a second voltage value of a second voltage source to the voltage supply nodes. The first voltage value and the second voltage value differ by a predetermined voltage value.

Abstract: A memory circuit includes a memory cell, a first bit line, a first bit line bar, a sense amplifier, a first switch and a second switch. The memory cell is coupled with a first bit line having a first bit line portion and a second bit line portion. The first bit line bar has a first bit line bar portion and a second bit line bar portion. The sense amplifier includes a read/write circuit configured to couple the second bit line portion to a global bit line. The first switch is coupled between the first bit line bar portion and the second bit line bar portion. The second switch is coupled between the first bit line portion and the second bit line portion.

Abstract: A memory controlling device includes: a control circuit arranged to generate a multi-pulse control signal with a first duration; and a memory cell coupled to a pair of bit lines and a word line, wherein the multi-pulse control signal is coupled to the word line, and the memory cell is arranged to output an output signal on the pair of bit lines during the first duration.

Abstract: A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal.

Abstract: A circuit includes a first memory cell and a data control circuit configured to provide first data and second data. The first memory cell has a first port and a second port. The first data is written from the first port to the first memory cell. The second data is based on information of the first data. The second port is configured to write the second data to the first memory cell based on a detection of a write disturb caused by the second port to the first port.

Abstract: A memory device includes: a memory array comprising a plurality of bits, wherein a first bit of the plurality of bits is coupled to a first assist circuit; a test engine, coupled to the memory array, and configured to examine whether each bit is functional; and an assist circuit trimming (ACT) circuit, coupled to the memory array and the test engine, and in response to the examination, configured to selectively activate the first assist circuit.

Abstract: A memory macro comprises a plurality of columns and a plurality of footers. A column of the plurality of columns comprises a plurality of nodes corresponding to a plurality of memory cells in the column. A footer of the plurality of footers corresponds to each column of the plurality of columns, is coupled with the plurality of nodes of the each column, and, in response to a column select signal of the plurality of columns, is configured to have a first current-sinking capability or a second current-sinking capability different from the first current-sinking capability.

Abstract: A circuit includes a memory cell having a first control line and a second control line, the first control line carrying a first control signal, the second control line carrying a second control signal. A first circuit is coupled to the first control line, the second control line, and a node, and a second circuit is coupled to the node and responds to a timing of the first control signal and the second control signal. The first circuit and the second circuit, based on the first control signal and the second control signal, are configured to generate a node signal on the node, and a logical value of the node signal indicates a write disturb condition of the memory cell.

Abstract: A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal.

Abstract: A memory device includes control line drivers coupled to respective pairs of reference supply voltage controllers and supply voltage controllers. The control line drivers are configured to apply control signals to the reference supply voltage controllers and the supply voltage controllers. For a read operation, the reference supply voltage controllers apply a first voltage to reference voltage supply nodes of un-accessed rows of the array of memory cells and a second voltage to accessed rows. A voltage level of the first voltage is greater than a voltage level of the second voltage. For a write operation, the supply voltage controllers apply a third voltage to un-accessed rows of the array of memory cells and a fourth voltage to accessed rows. A voltage level of the third voltage is greater than a voltage level of the fourth voltage.

Abstract: A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value flowing through the transistor is determined when the transistor is in on. A first reference voltage value at a reference node of the memory cell when the transistor is off is higher than a second reference voltage value at the reference node when the transistor is on. Based on the first current value, the second current value, and a relationship between the first current value and the second current value, a number of memory cells to be coupled with a data line associated with the memory cell is determined.

Abstract: A method of controlling a wordline by a driver decoder circuit includes generating a first control signal having a first logically high level and a first logically low level, and generating a second control signal having a second logically high level when the first control signal has the first logically high level and a second logically low level when the first control signal has the first logically low level. The first logically high level is different from the second logically high level, and the first logically low level is different from the second logically low level. The method includes coupling the wordline to a first node having a first voltage value in response to the first control signal having the first logically low level and decoupling the wordline from a second node having a second voltage value in response to the second control signal having the second logically low level.

Abstract: A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The first transistor and the second transistor form an inverter. The third transistor is coupled with an output of the inverter. The circuit includes at least one of the following voltage sources: a first voltage source, a second voltage source, and a third voltage source. The first voltage source is coupled with a bulk of the first transistor, and is different from a first supply voltage source of the first transistor. T second voltage source is coupled with a bulk of the second transistor, and is different from a second supply voltage of the second transistor. The third voltage source is coupled with a bulk of the third transistor.

Abstract: A device layout tool includes a gate electrode layer, wherein the gate electrode layer is configured to define a three dimensional gate structure over a fin structure, wherein the fin structure has three exposed surfaces. The device layout tool further includes a defect-describing layer, wherein the defect-describing layer is configured to define locations of gate defects relative to the three exposed surfaces of the fin structure.

Abstract: A circuit includes a first transistor and a second transistor of a first type. The circuit further includes a first transistor of a second type. A first first-type drain is coupled to a second first-type source. A first first-type source is configured to have a first voltage value. A first first-type gate is configured to have a first control signal. A second first-type drain is configured to serve as a wordline. A second first-type gate is configured to have a second voltage value. A first second-type source is configured to have a third voltage value. A first second-type gate is configured to have a second control signal. The first transistor and the second transistor of the first type are configured to provide the first voltage value for the wordline. The first transistor of the second-type is configured to provide the third voltage value the wordline.

Abstract: A memory macro comprises a plurality of columns and a plurality of footers. A column of the plurality of columns comprises a plurality of nodes corresponding to a plurality of memory cells in the column. A footer of the plurality of footers corresponds to each column of the plurality of columns, is coupled with the plurality of nodes of the each column, and, in response to a column select signal of the plurality of columns, is configured to have a first current-sinking capability or a second current-sinking capability different from the first current-sinking capability.

Abstract: A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.

Abstract: A circuit includes a memory cell, a first data line, a second data line, and a clamping unit. The memory cell includes a data node, a first pass gate, and a second pass gate. The first pass gate is between the first data line and the data node. The second pass gate is between the second data line and the data node. The clamping unit is electrically coupled to the first data line and configured to pull a voltage level of the first data line toward a clamped voltage level when the clamping unit is enabled, and to function as an open circuit to the first data line when the clamping unit is disabled. The clamping unit is disabled when a first control signal indicates that a voltage level of the second data line is pulled toward a reference voltage level.