Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.

Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on a first read operation on the flash memory with a first reference voltage. The circuit may be configured to generate soft information based on the estimated slope information. The circuit may be configured to decode a result of a second read operation on the flash memory based on the soft information.

Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations of the flash memory. The circuit may be configured to estimate slope information of a plurality of threshold voltage samples based on soft decoding errors in connection with a first read operation on the flash memory. The circuit may be further configured to generate estimated soft information based on the estimated slope information. The circuit may be further configured to decode a result of a second read operation on the flash memory based on the estimated soft information.

Abstract: Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

Abstract: Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.

Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.

Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.

Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.

Abstract: A method for multi-dimensional decoding, the method may include receiving a multi-dimensional encoded codeword that comprises a payload and a redundancy section; wherein the payload comprises data and an error detection process signature; evaluating, during a multi-dimensional decoding process of the multi-dimensional encoded codeword, an hypothesis regarding a content of the payload; applying on the hypotheses an error detection process to provide an indication about a validity of the hypotheses; and proceeding with the multi-dimensional decoding process and finding a next hypothesis to be error detection process validated when the hypothesis is invalid.

Abstract: A flash memory system may include a cell flash memory and a circuit for performing operations of the plurality of cells. The cell flash memory may have a plurality of cells. The circuit may be configured to estimate an interference state based on a result of a read operation on a first neighboring cell of a first cell among the plurality of cells. The circuit may be configured to perform a read operation on the first cell. The circuit may be configured to generate soft information based on a result of the read operation and the interference state. The circuit may be configured to decode the result of the read operation on the first cell based on the soft information.

Abstract: A flash memory system may include a cell flash memory having a plurality of threshold voltages, and a circuit for performing operations of the cell flash memory. The circuit may perform a first read operation on a first cell of the cell flash memory with a first threshold voltage among the plurality of threshold voltages, estimate a first interference state relating to the first threshold voltage, estimate a first voltage shift based on the first interference state, and perform a first shifted read operation on the first cell of the cell flash memory with a shifted first threshold voltage shifted with the first voltage shift, generate a first decoder input based on the estimated first interference state and the result of the first shifted read operation on the first cell, and decode, based on the first decoder input, a result of the first read operation on the first cell.

Abstract: The present embodiments relate to methods for estimating bit error rates (BERs) associated with a flash memory. According to certain aspects, embodiments provide estimating the BER of multi-bit flash memories during the programming of the flash memory, and providing the estimated BER in a readable status register of the flash memory, thereby improving the speed of programming of the flash memory.

Abstract: A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.

Abstract: An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

Abstract: A method for fast decoding, the method may include (a) performing a hard read of a group of flash memory cells to provide hard read data; wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions; (b) hard decoding the hard read data to provide a hard decoding result; wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions; (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data; (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result; and (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.

Abstract: An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

Abstract: System and method for facilitating real-time detection and notification of events are disclosed. The system comprises a sensor module, a controller and a display module. The sensor module senses an occurrence of an event in proximity of a user engaged in viewing content displayed on a screen of an electronic device, and generates a signal representing the occurrence of the event. The controller determines whether a characteristic of the signal is greater than a predetermined threshold value and generates a notification if the characteristic of the signal is determined to be greater than the predetermined threshold value. The display module overlays the notification on the screen of the electronic device to alert the user of the occurrence of the event.

Abstract: A method for interleaved multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the group of bits; and encoding the first and second versions of the groups of bits in an interleaved manner; wherein the encoding comprises calculating at least one codeword component of the first version by encoding a set of bits of the first version and at least a portion of a redundancy of at least one data entity of the second version and calculating at least one codeword component of the second version by encoding a set of bits of the second version and at least a portion of a redundancy of at least one data entity of the first version.