Abstract: A method for wear reduction of a flash memory module, the method may include reading data stored in a group of flash memory cells to provide a read data; wherein the reading comprise supplying a bias voltage that is lower than a write bias voltage; wherein the write bias voltage was supplied to the group of flash memory cells during a writing of the data to the group of flash memory cells; and decoding the read data, by applying a decoding process of a given complexity, to provide decoded data.

Abstract: A method for parallel multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.

Abstract: A method for non-uniform multiple dimensional decoding, the method may include receiving or generating a multiple dimensional encoded data unit; and decoding by a processor the multiple dimensional encoded data unit to provide a decoded data unit; wherein the multiple dimensional encoded data unit comprises multiple component codes associated with multiple dimensions; wherein the multiple dimensions comprise a plurality of non-uniform dimensions; wherein at least two component codes of each non-uniform dimension differ from each other by encoding rate; wherein the decoding is responsive to encoding rates of component codes of the plurality of non-uniform dimensions.

Abstract: A flash memory module and a method for programming a page of flash memory cells, the method includes: receiving a cycle count indication indicative of a number of program cycles of the page of memory cells; setting a value of a programming parameter of a programming operation based on the cycle count indication; and programming at least one flash memory cell of the page of flash memory cells by performing the programming operation.

Abstract: A method of decoding an array of multi-dimensional code components, the method may include searching in a group of multi-dimensional code components a suspected multi-dimensional code component, wherein the suspected multi-dimensional code component belongs to the array multi-dimensional code components and is associated with a false correction probability that exceeds a false correction threshold; wherein the searching comprises dummy decoding, by a decoder, the group of multi-dimensional code components; and performing at least one non-dummy decoding of multi-dimensional code components of the array without performing non-dummy decoding of the suspected multi-dimensional code component.

Abstract: A system, computer readable medium and a method for multi-dimensional decoding.

Abstract: A computer readable medium, a system and a method for flash memory device parameter optimization, the method may include: receiving or generating an estimate of a wear level of at least one group of flash memory cells of the flash memory device, and finding erase parameters and programming parameters to be applied on one or more groups of flash memory cells of the flash memory device in response to estimate of the wear level.

Abstract: A system, a method and a non-transitory computer readable medium for generating soft information. The method may include performing a first set of read attempts of flash memory cells using a first set of read thresholds to provide first read results; calculating for each flash memory cell in response to the first read results, first cell information indicative of a first change-inducing read threshold; performing a second set of read attempts of the flash memory cells using a second set of read thresholds to provide second read results, calculating for each flash memory cell in response to the second read results, second cell information indicative of a second change-inducing read threshold; and generating, for each flash memory cell soft information in response to the first cell information and the second cell information of the flash memory cell.

Abstract: A flash memory controller, a computer readable medium and a method. The method may include performing, by a flash memory controller, multiple read attempts of a group of flash memory cells, using multiple read thresholds, to provide multiple read results; determining, by the flash memory controller and based upon the multiple read results, a reliability metric of each of the multiple read results; and error correction decoding the multiple read results based upon reliability metrics associated with the multiple read results.

Abstract: A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.

Abstract: A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate.

Abstract: A decoder, an encoder, a decoding method and an encoding method are provided. The encoding method includes receiving data; generating a set of first codewords by applying a first encoding process on the received data; and performing a second encoding process on a folded version of each first codeword to provide a set of second codewords, wherein a folded version of a first codeword is representative of a storage of the first codeword in a two dimensional memory space, wherein the second codeword comprises redundancy bits.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.

Abstract: A system, method and computer readable medium for programming and reading flash memory cells. Respective first and second read operations may be performed while supplying respective first and second bias voltage to multiple flash memory cells, to provide respective first and second read results, where the first bias voltage may be higher then the second bias voltage, and providing a read outcome that may be responsive to the first read results and to the second read results. A programming method may include performing first and second programming operations while supplying respective first and second bias voltages to multiple flash memory cells. The programming method may further include performing the first programming operation while programming information mapped to a highest least significant bit positive lobe, and performing the second programming operation while programming information mapped to at least one other least significant bit positive lobe.

Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.

Abstract: A device, method, and computer readable medium for programming a codeword are presented. The method includes writing a first codeword portion to portions of nonvolatile memory rows, and writing a second codeword portion to portions of nonvolatile memory rows, wherein the first group of memory rows and the second group belong to non-overlapping groups. The device includes multiple nonvolatile memory rows, and a controller receiving a codeword comprising a first codeword portion and a second codeword portion. The controller writing the first codeword portion to portions of nonvolatile memory rows, and writing the second codeword portion to portions of nonvolatile memory rows, wherein the first group of nonvolatile memory rows differs and the second group of nonvolatile memory rows belong to non-overlapping groups, and the first and second groups of memory rows belong to multiple rows. A computer readable medium having stored thereon instructions performing methods described herein.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: Wireless network system including a plurality of base stations each configured to manage active links to mobile stations within a range; and a controller configured to control the base stations to provide at least two of the active links from two different base stations simultaneously to a given mobile station in integral manner for joint processing.

Abstract: Embodiments of the invention are directed to managing a memory component. A method may include performing a first erase operation according to a first set of erase parameters, determining a result of the first erase operation, modifying the first set erase parameters based on the result to produce a second set of erase parameters and performing a second erase operation according to a second set of erase parameters. A condition parameter may be maintained based on the erased parameters and/or based on a result of an erase procedure.