Abstract: A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P.sup.- surface of a semiconductor substrate almost to a buried N.sup.+ layer. The floor of one trench is heavily N-doped to establish a connection between the buried N.sup.+ layer and an N.sup.- diffusion in the walls of the trench. When the trenches are backfilled with P.sup.+ polysilicon a lateral PNP is formed having a buried base contact.

Abstract: A method or process is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and an opening in an insulating layer disposed on the surface of the semiconductor body. A trench is then formed in the semiconductor layer having a sidewall located along a given plane through the opening and through the P/N junction. An insulating material is disposed within the trench and over the insulating layer and a block or segment of material is located over the trench so as to extend a given distance from the trench over the upper surface of the body. The insulating material and the block are then etched so as to remove the block and the insulating material located along the sides of the block. A layer of low viscosity material is formed over the semiconductor body so as to cover the remaining portion of the insulating material, the layer of low viscosity material and the insulating material having similar etch rates.

Abstract: A method for fabrication of a buried field shield in a semiconductor substrate. A seed substrate is prepared by depositing an epitaxial layer or a seed wafer and then depositing a heavily doped layer and a thin dielectric. The thin dielectric is patterned for contact holes and then a conductive field shield is deposited and patterned. A thick quartz layer is deposited over the field shield and dielectric. A mechanical substrate is anodically bonded to the quartz of the seed substrate and the original seed wafer is etched back to expose the epitaxial layer for further fabrication.

Abstract: This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.

Abstract: This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP transistor. By using the PNP transistor as a read transistor and the NPN as a write transistor, the cell, when made in integrated form, utilizes the cell isolation capacitance to enhance the stored information without increasing the parasitic capacitances in the cell. This cell isolation capacitance can be enhanced by trenching between each cell in the array, oxidizing the trench walls and backfilling the trench with semiconductor material thereby obtaining greater contrast between 0 and 1 signals. This cell is especially useful in memory arrays.